From 607795f9177da6905c2888baf7452cad09da86aa Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Fri, 19 Mar 2010 04:14:21 +0000 Subject: [PATCH] comment out a bunch of parallel store patterns that apparently can't match or just have no testcases. Will remove after confirmation from dan that they really are dead. llvm-svn: 98930 --- llvm/lib/Target/X86/X86Instr64bit.td | 26 ++++++++++++++++++---- llvm/lib/Target/X86/X86InstrInfo.td | 32 +++++++++++++++++++--------- 2 files changed, 44 insertions(+), 14 deletions(-) diff --git a/llvm/lib/Target/X86/X86Instr64bit.td b/llvm/lib/Target/X86/X86Instr64bit.td index 81fc0671c4e5..d54851217f8f 100644 --- a/llvm/lib/Target/X86/X86Instr64bit.td +++ b/llvm/lib/Target/X86/X86Instr64bit.td @@ -2224,7 +2224,7 @@ def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2), def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)), (implicit EFLAGS)), (ADD64rm GR64:$src1, addr:$src2)>; - +/* // Memory-Register Addition with EFLAGS result def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2), addr:$dst), @@ -2239,6 +2239,7 @@ def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), addr:$dst), (implicit EFLAGS)), (ADD64mi32 addr:$dst, i64immSExt32:$src2)>; +*/ // Register-Register Subtraction with EFLAGS result def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2), @@ -2258,6 +2259,7 @@ def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2), (implicit EFLAGS)), (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>; +/* // Memory-Register Subtraction with EFLAGS result def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2), addr:$dst), @@ -2275,6 +2277,7 @@ def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), addr:$dst), (implicit EFLAGS)), (SUB64mi32 addr:$dst, i64immSExt32:$src2)>; +*/ // Register-Register Signed Integer Multiplication with EFLAGS result def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2), @@ -2305,36 +2308,45 @@ def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2), // INC and DEC with EFLAGS result. Note that these do not set CF. def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>; +/* def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst), (implicit EFLAGS)), - (INC64_16m addr:$dst)>, Requires<[In64BitMode]>; + (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;*/ def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>; +/* def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst), (implicit EFLAGS)), - (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>; + (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;*/ def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>; +/* def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst), (implicit EFLAGS)), - (INC64_32m addr:$dst)>, Requires<[In64BitMode]>; + (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;*/ def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>; +/* def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst), (implicit EFLAGS)), (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>; +*/ def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)), (INC64r GR64:$src)>; +/* def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst), (implicit EFLAGS)), (INC64m addr:$dst)>; + */ def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)), (DEC64r GR64:$src)>; +/* def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst), (implicit EFLAGS)), (DEC64m addr:$dst)>; + */ // Register-Register Logical Or with EFLAGS result def : Pat<(parallel (X86or_flag GR64:$src1, GR64:$src2), @@ -2355,6 +2367,7 @@ def : Pat<(parallel (X86or_flag GR64:$src1, (loadi64 addr:$src2)), (OR64rm GR64:$src1, addr:$src2)>; // Memory-Register Logical Or with EFLAGS result +/* def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), GR64:$src2), addr:$dst), (implicit EFLAGS)), @@ -2367,6 +2380,7 @@ def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt32:$src2), addr:$dst), (implicit EFLAGS)), (OR64mi32 addr:$dst, i64immSExt32:$src2)>; +*/ // Register-Register Logical XOr with EFLAGS result def : Pat<(parallel (X86xor_flag GR64:$src1, GR64:$src2), @@ -2387,6 +2401,7 @@ def : Pat<(parallel (X86xor_flag GR64:$src1, (loadi64 addr:$src2)), (XOR64rm GR64:$src1, addr:$src2)>; // Memory-Register Logical XOr with EFLAGS result +/* def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), GR64:$src2), addr:$dst), (implicit EFLAGS)), @@ -2400,6 +2415,7 @@ def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), addr:$dst), (implicit EFLAGS)), (XOR64mi32 addr:$dst, i64immSExt32:$src2)>; +*/ // Register-Register Logical And with EFLAGS result def : Pat<(parallel (X86and_flag GR64:$src1, GR64:$src2), @@ -2420,6 +2436,7 @@ def : Pat<(parallel (X86and_flag GR64:$src1, (loadi64 addr:$src2)), (AND64rm GR64:$src1, addr:$src2)>; // Memory-Register Logical And with EFLAGS result +/* def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), GR64:$src2), addr:$dst), (implicit EFLAGS)), @@ -2433,6 +2450,7 @@ def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), addr:$dst), (implicit EFLAGS)), (AND64mi32 addr:$dst, i64immSExt32:$src2)>; +*/ //===----------------------------------------------------------------------===// // X86-64 SSE Instructions diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 7b839da243e1..630ccb1ee5e8 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -4784,6 +4784,7 @@ def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2), (implicit EFLAGS)), (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; +/* // Memory-Register Addition with EFLAGS result def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2), addr:$dst), @@ -4819,6 +4820,7 @@ def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2), addr:$dst), (implicit EFLAGS)), (ADD32mi8 addr:$dst, i32immSExt8:$src2)>; +*/ // Register-Register Subtraction with EFLAGS result def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2), @@ -4859,6 +4861,7 @@ def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2), (implicit EFLAGS)), (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; +/* // Memory-Register Subtraction with EFLAGS result def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2), addr:$dst), @@ -4894,7 +4897,7 @@ def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2), addr:$dst), (implicit EFLAGS)), (SUB32mi8 addr:$dst, i32immSExt8:$src2)>; - +*/ // Register-Register Signed Integer Multiply with EFLAGS result def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2), @@ -4954,36 +4957,40 @@ def : Pat<(parallel (X86smul_flag GR32:$src1, 2), // INC and DEC with EFLAGS result. Note that these do not set CF. def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)), (INC8r GR8:$src)>; + /* def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst), (implicit EFLAGS)), (INC8m addr:$dst)>; + */ def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)), (DEC8r GR8:$src)>; -def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst), +/*def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst), (implicit EFLAGS)), - (DEC8m addr:$dst)>; + (DEC8m addr:$dst)>;*/ def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)), (INC16r GR16:$src)>, Requires<[In32BitMode]>; +/* def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst), (implicit EFLAGS)), - (INC16m addr:$dst)>, Requires<[In32BitMode]>; + (INC16m addr:$dst)>, Requires<[In32BitMode]>;*/ def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)), (DEC16r GR16:$src)>, Requires<[In32BitMode]>; +/* def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst), (implicit EFLAGS)), - (DEC16m addr:$dst)>, Requires<[In32BitMode]>; + (DEC16m addr:$dst)>, Requires<[In32BitMode]>;*/ def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)), (INC32r GR32:$src)>, Requires<[In32BitMode]>; -def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst), +/*def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst), (implicit EFLAGS)), - (INC32m addr:$dst)>, Requires<[In32BitMode]>; + (INC32m addr:$dst)>, Requires<[In32BitMode]>;*/ def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)), (DEC32r GR32:$src)>, Requires<[In32BitMode]>; -def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst), +/*def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst), (implicit EFLAGS)), - (DEC32m addr:$dst)>, Requires<[In32BitMode]>; + (DEC32m addr:$dst)>, Requires<[In32BitMode]>;*/ // Register-Register Or with EFLAGS result def : Pat<(parallel (X86or_flag GR8:$src1, GR8:$src2), @@ -5023,7 +5030,7 @@ def : Pat<(parallel (X86or_flag GR16:$src1, i16immSExt8:$src2), def : Pat<(parallel (X86or_flag GR32:$src1, i32immSExt8:$src2), (implicit EFLAGS)), (OR32ri8 GR32:$src1, i32immSExt8:$src2)>; - +/* // Memory-Register Or with EFLAGS result def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), GR8:$src2), addr:$dst), @@ -5059,6 +5066,7 @@ def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), i32immSExt8:$src2), addr:$dst), (implicit EFLAGS)), (OR32mi8 addr:$dst, i32immSExt8:$src2)>; + */ // Register-Register XOr with EFLAGS result def : Pat<(parallel (X86xor_flag GR8:$src1, GR8:$src2), @@ -5099,6 +5107,7 @@ def : Pat<(parallel (X86xor_flag GR32:$src1, i32immSExt8:$src2), (implicit EFLAGS)), (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; +/* // Memory-Register XOr with EFLAGS result def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), GR8:$src2), addr:$dst), @@ -5134,6 +5143,7 @@ def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), i32immSExt8:$src2), addr:$dst), (implicit EFLAGS)), (XOR32mi8 addr:$dst, i32immSExt8:$src2)>; +*/ // Register-Register And with EFLAGS result def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2), @@ -5174,6 +5184,7 @@ def : Pat<(parallel (X86and_flag GR32:$src1, i32immSExt8:$src2), (implicit EFLAGS)), (AND32ri8 GR32:$src1, i32immSExt8:$src2)>; +/* // Memory-Register And with EFLAGS result def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), GR8:$src2), addr:$dst), @@ -5209,6 +5220,7 @@ def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), i32immSExt8:$src2), addr:$dst), (implicit EFLAGS)), (AND32mi8 addr:$dst, i32immSExt8:$src2)>; +*/ // -disable-16bit support. def : Pat<(truncstorei16 (i16 imm:$src), addr:$dst),