[AArch64][SVE] Asm: Extend EnforceVectorSubVectorTypeIs to distinguish Scalable Vectors
Patch [1/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions. Patch by Sander De Smalen. Reviewed by: rengolin Differential Revision: https://reviews.llvm.org/D39087 llvm-svn: 317564
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@ -603,6 +603,11 @@ bool TypeInfer::EnforceVectorSubVectorTypeIs(TypeSetByHwMode &Vec,
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auto IsSubVec = [](MVT B, MVT P) -> bool {
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if (!B.isVector() || !P.isVector())
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return false;
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// Logically a <4 x i32> is a valid subvector of <n x 4 x i32>
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// but until there are obvious use-cases for this, keep the
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// types separate.
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if (B.isScalableVector() != P.isScalableVector())
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return false;
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if (B.getVectorElementType() != P.getVectorElementType())
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return false;
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return B.getVectorNumElements() < P.getVectorNumElements();
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