AMDGPU/GlobalISel: Insert waterfall loop for vector indexing
The register index can only really be an SGPR. Lie that a VGPR index is legal, and then rewrite the instruction in a waterfall loop to handle the index. llvm-svn: 357235
This commit is contained in:
Matt Arsenault
parent
1445b77e8c
commit
5fddf09187
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@ -13,9 +13,11 @@
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#include "AMDGPURegisterBankInfo.h"
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#include "AMDGPUInstrInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "SIMachineFunctionInfo.h"
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#include "SIRegisterInfo.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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@ -328,6 +330,170 @@ static LLT getHalfSizedType(LLT Ty) {
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return LLT::scalar(Ty.getSizeInBits() / 2);
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}
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/// Legalize instruction \p MI where operands in \p OpIndices must be SGPRs. If
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/// any of the required SGPR operands are VGPRs, perform a waterfall loop to
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/// execute the instruction for each unique combination of values in all lanes
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/// in the wave. The block will be split such that new blocks
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void AMDGPURegisterBankInfo::executeInWaterfallLoop(
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MachineInstr &MI, MachineRegisterInfo &MRI,
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ArrayRef<unsigned> OpIndices) const {
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MachineFunction *MF = MI.getParent()->getParent();
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const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
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const SIInstrInfo *TII = ST.getInstrInfo();
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MachineBasicBlock::iterator I(MI);
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MachineBasicBlock &MBB = *MI.getParent();
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const DebugLoc &DL = MI.getDebugLoc();
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assert(OpIndices.size() == 1 &&
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"need to implement support for multiple operands");
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// Use a set to avoid extra readfirstlanes in the case where multiple operands
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// are the same register.
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SmallSet<unsigned, 4> SGPROperandRegs;
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for (unsigned Op : OpIndices) {
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assert(MI.getOperand(Op).isUse());
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unsigned Reg = MI.getOperand(Op).getReg();
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const RegisterBank *OpBank = getRegBank(Reg, MRI, *TRI);
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if (OpBank->getID() == AMDGPU::VGPRRegBankID)
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SGPROperandRegs.insert(Reg);
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}
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// No operands need to be replaced, so no need to loop.
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if (SGPROperandRegs.empty())
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return;
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MachineIRBuilder B(MI);
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SmallVector<unsigned, 4> ResultRegs;
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SmallVector<unsigned, 4> InitResultRegs;
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SmallVector<unsigned, 4> PhiRegs;
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for (MachineOperand &Def : MI.defs()) {
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LLT ResTy = MRI.getType(Def.getReg());
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const RegisterBank *DefBank = getRegBank(Def.getReg(), MRI, *TRI);
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ResultRegs.push_back(Def.getReg());
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unsigned InitReg = B.buildUndef(ResTy).getReg(0);
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unsigned PhiReg = MRI.createGenericVirtualRegister(ResTy);
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InitResultRegs.push_back(InitReg);
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PhiRegs.push_back(PhiReg);
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MRI.setRegBank(PhiReg, *DefBank);
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MRI.setRegBank(InitReg, *DefBank);
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}
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unsigned SaveExecReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
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unsigned InitSaveExecReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
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// Don't bother using generic instructions/registers for the exec mask.
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B.buildInstr(TargetOpcode::IMPLICIT_DEF)
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.addDef(InitSaveExecReg);
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// Save the EXEC mask
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BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B64_term), SaveExecReg)
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.addReg(AMDGPU::EXEC);
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unsigned PhiExec = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
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unsigned NewExec = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
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unsigned CondReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
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// To insert the loop we need to split the block. Move everything before this
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// point to a new block, and insert a new empty block before this instruction.
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MachineBasicBlock *LoopBB = MF->CreateMachineBasicBlock();
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MachineBasicBlock *RemainderBB = MF->CreateMachineBasicBlock();
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MachineBasicBlock *RestoreExecBB = MF->CreateMachineBasicBlock();
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MachineFunction::iterator MBBI(MBB);
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++MBBI;
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MF->insert(MBBI, LoopBB);
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MF->insert(MBBI, RestoreExecBB);
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MF->insert(MBBI, RemainderBB);
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LoopBB->addSuccessor(RestoreExecBB);
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LoopBB->addSuccessor(LoopBB);
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// Move the rest of the block into a new block.
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RemainderBB->transferSuccessorsAndUpdatePHIs(&MBB);
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RemainderBB->splice(RemainderBB->begin(), &MBB, I, MBB.end());
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MBB.addSuccessor(LoopBB);
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RestoreExecBB->addSuccessor(RemainderBB);
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B.setInsertPt(*LoopBB, LoopBB->end());
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B.buildInstr(TargetOpcode::PHI)
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.addDef(PhiExec)
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.addReg(InitSaveExecReg)
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.addMBB(&MBB)
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.addReg(NewExec)
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.addMBB(LoopBB);
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for (auto Result : zip(InitResultRegs, ResultRegs, PhiRegs)) {
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B.buildInstr(TargetOpcode::G_PHI)
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.addDef(std::get<2>(Result))
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.addReg(std::get<0>(Result)) // Initial value / implicit_def
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.addMBB(&MBB)
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.addReg(std::get<1>(Result)) // Mid-loop value.
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.addMBB(LoopBB);
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}
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// Move the instruction into the loop.
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LoopBB->splice(LoopBB->end(), &MBB, I);
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I = std::prev(LoopBB->end());
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for (MachineOperand &Op : MI.uses()) {
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if (!Op.isReg())
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continue;
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assert(!Op.isDef());
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if (SGPROperandRegs.count(Op.getReg())) {
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unsigned CurrentLaneOpReg
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= MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
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MRI.setType(CurrentLaneOpReg, LLT::scalar(32)); // FIXME
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assert(MRI.getType(Op.getReg())== LLT::scalar(32) &&
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"need to implement support for other types");
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constrainGenericRegister(Op.getReg(), AMDGPU::VGPR_32RegClass, MRI);
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// Read the next variant <- also loop target.
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BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
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CurrentLaneOpReg)
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.addReg(Op.getReg());
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// FIXME: Need to and each conditon
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// Compare the just read SGPR value to all possible operand values.
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B.buildInstr(AMDGPU::V_CMP_EQ_U32_e64)
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.addDef(CondReg)
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.addReg(CurrentLaneOpReg)
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.addReg(Op.getReg());
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Op.setReg(CurrentLaneOpReg);
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}
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}
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// Update EXEC, save the original EXEC value to VCC.
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B.buildInstr(AMDGPU::S_AND_SAVEEXEC_B64)
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.addDef(NewExec)
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.addReg(CondReg, RegState::Kill);
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MRI.setSimpleHint(NewExec, CondReg);
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// Update EXEC, switch all done bits to 0 and all todo bits to 1.
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B.buildInstr(AMDGPU::S_XOR_B64_term)
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.addDef(AMDGPU::EXEC)
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.addReg(AMDGPU::EXEC)
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.addReg(NewExec);
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// XXX - s_xor_b64 sets scc to 1 if the result is nonzero, so can we use
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// s_cbranch_scc0?
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// Loop back to V_READFIRSTLANE_B32 if there are still variants to cover.
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B.buildInstr(AMDGPU::S_CBRANCH_EXECNZ)
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.addMBB(LoopBB);
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// Restore the EXEC mask
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B.buildInstr(AMDGPU::S_MOV_B64_term)
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.addDef(AMDGPU::EXEC)
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.addReg(SaveExecReg);
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}
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void AMDGPURegisterBankInfo::applyMappingImpl(
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const OperandsMapper &OpdMapper) const {
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MachineInstr &MI = OpdMapper.getMI();
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@ -436,6 +602,10 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
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MI.eraseFromParent();
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return;
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}
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case AMDGPU::G_EXTRACT_VECTOR_ELT:
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applyDefaultMapping(OpdMapper);
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executeInWaterfallLoop(MI, MRI, { 2 });
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return;
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default:
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break;
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}
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@ -37,6 +37,10 @@ protected:
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class AMDGPURegisterBankInfo : public AMDGPUGenRegisterBankInfo {
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const SIRegisterInfo *TRI;
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void executeInWaterfallLoop(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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ArrayRef<unsigned> OpIndices) const;
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/// See RegisterBankInfo::applyMapping.
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void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
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@ -3,13 +3,15 @@
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
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---
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name: extract_vector_elt_v16i32_ss
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name: extract_vector_elt_v16s32_ss
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16
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; CHECK-LABEL: name: extract_vector_elt_v16i32_ss
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; CHECK-LABEL: name: extract_vector_elt_v16s32_ss
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; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16
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; CHECK: [[COPY:%[0-9]+]]:sgpr(<16 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr16
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; CHECK: [[EVEC:%[0-9]+]]:sgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<16 x s32>), [[COPY1]](s32)
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@ -21,17 +23,36 @@ body: |
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...
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---
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name: extract_vector_elt_v16i32_sv
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name: extract_vector_elt_v16s32_sv
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $vgpr0
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; CHECK-LABEL: name: extract_vector_elt_v16i32_sv
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; CHECK-LABEL: name: extract_vector_elt_v16s32_sv
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:sgpr(<16 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(<16 x s32>) = COPY [[COPY]](<16 x s32>)
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; CHECK: [[EVEC:%[0-9]+]]:vgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY2]](<16 x s32>), [[COPY1]](s32)
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; CHECK: [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF
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; CHECK: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
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; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
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; CHECK: .1:
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; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK: [[PHI:%[0-9]+]]:sreg_64 = PHI [[DEF1]], %bb.0, %9, %bb.1
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; CHECK: [[PHI1:%[0-9]+]]:vgpr(s32) = G_PHI [[DEF]](s32), %bb.0, %2(s32), %bb.1
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; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
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; CHECK: [[EVEC:%[0-9]+]]:vgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY2]](<16 x s32>), [[V_READFIRSTLANE_B32_]](s32)
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; CHECK: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]](s32), [[COPY1]](s32), implicit $exec
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; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[V_CMP_EQ_U32_e64_]], implicit-def $exec, implicit-def $scc, implicit $exec
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; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
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; CHECK: S_CBRANCH_EXECNZ %bb.1, implicit $exec
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; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
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; CHECK: .2:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: .3:
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; CHECK: $vgpr0 = COPY [[EVEC]](s32)
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%0:_(<16 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
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%1:_(s32) = COPY $vgpr0
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@ -40,13 +61,15 @@ body: |
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...
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---
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name: extract_vector_elt_v16i32_vs
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name: extract_vector_elt_v16s32_vs
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $sgpr0
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; CHECK-LABEL: name: extract_vector_elt_v16i32_vs
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; CHECK-LABEL: name: extract_vector_elt_v16s32_vs
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; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $sgpr0
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; CHECK: [[COPY:%[0-9]+]]:vgpr(<16 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[EVEC:%[0-9]+]]:vgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<16 x s32>), [[COPY1]](s32)
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@ -58,19 +81,75 @@ body: |
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...
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---
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name: extract_vector_elt_v16i32_vv
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name: extract_vector_elt_v16s32_vv
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16
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; CHECK-LABEL: name: extract_vector_elt_v16i32_vv
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; CHECK-LABEL: name: extract_vector_elt_v16s32_vv
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16
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; CHECK: [[COPY:%[0-9]+]]:vgpr(<16 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr16
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; CHECK: [[EVEC:%[0-9]+]]:vgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<16 x s32>), [[COPY1]](s32)
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; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr16
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; CHECK: [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF
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; CHECK: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
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; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
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; CHECK: .1:
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; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK: [[PHI:%[0-9]+]]:sreg_64 = PHI [[DEF1]], %bb.0, %8, %bb.1
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; CHECK: [[PHI1:%[0-9]+]]:vgpr(s32) = G_PHI [[DEF]](s32), %bb.0, %2(s32), %bb.1
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; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
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; CHECK: [[EVEC:%[0-9]+]]:vgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<16 x s32>), [[V_READFIRSTLANE_B32_]](s32)
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; CHECK: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]](s32), [[COPY1]](s32), implicit $exec
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; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[V_CMP_EQ_U32_e64_]], implicit-def $exec, implicit-def $scc, implicit $exec
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; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
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; CHECK: S_CBRANCH_EXECNZ %bb.1, implicit $exec
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; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
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; CHECK: .2:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: .3:
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; CHECK: $vgpr0 = COPY [[EVEC]](s32)
|
||||
%0:_(<16 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
||||
%1:_(s32) = COPY $vgpr16
|
||||
%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
|
||||
$vgpr0 = COPY %2
|
||||
...
|
||||
|
||||
---
|
||||
name: extract_vector_elt_v8s64_vv
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16
|
||||
; CHECK-LABEL: name: extract_vector_elt_v8s64_vv
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(<8 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr16
|
||||
; CHECK: [[DEF:%[0-9]+]]:vgpr(s64) = G_IMPLICIT_DEF
|
||||
; CHECK: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK: .1:
|
||||
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; CHECK: [[PHI:%[0-9]+]]:sreg_64 = PHI [[DEF1]], %bb.0, %8, %bb.1
|
||||
; CHECK: [[PHI1:%[0-9]+]]:vgpr(s64) = G_PHI [[DEF]](s64), %bb.0, %2(s64), %bb.1
|
||||
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
|
||||
; CHECK: [[EVEC:%[0-9]+]]:vgpr(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<8 x s64>), [[V_READFIRSTLANE_B32_]](s32)
|
||||
; CHECK: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]](s32), [[COPY1]](s32), implicit $exec
|
||||
; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[V_CMP_EQ_U32_e64_]], implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
|
||||
; CHECK: S_CBRANCH_EXECNZ %bb.1, implicit $exec
|
||||
; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK: .2:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: .3:
|
||||
; CHECK: $vgpr0_vgpr1 = COPY [[EVEC]](s64)
|
||||
%0:_(<8 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
||||
%1:_(s32) = COPY $vgpr16
|
||||
%2:_(s64) = G_EXTRACT_VECTOR_ELT %0, %1
|
||||
$vgpr0_vgpr1 = COPY %2
|
||||
...
|
||||
|
|
|
|||
Loading…
Reference in New Issue