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getValueType().getScalarSizeInBits() -> getScalarValueSizeInBits() ; NFCI 

llvm-svn: 281490
This commit is contained in:
Sanjay Patel 2016-09-14 15:43:44 +00:00
parent bd6fca1419
commit 5f6bb6cd24
7 changed files with 42 additions and 57 deletions
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56
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -181,7 +181,7 @@ namespace {
/// if things it uses can be simplified by bit propagation. /// if things it uses can be simplified by bit propagation.
/// If so, return true. /// If so, return true.
bool SimplifyDemandedBits(SDValue Op) { bool SimplifyDemandedBits(SDValue Op) {
unsigned BitWidth = Op.getValueType().getScalarSizeInBits(); unsigned BitWidth = Op.getScalarValueSizeInBits();
APInt Demanded = APInt::getAllOnesValue(BitWidth); APInt Demanded = APInt::getAllOnesValue(BitWidth);
return SimplifyDemandedBits(Op, Demanded); return SimplifyDemandedBits(Op, Demanded);
} }
@ -3080,16 +3080,12 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
// fold (and x, 0) -> 0, vector edition // fold (and x, 0) -> 0, vector edition
if (ISD::isBuildVectorAllZeros(N0.getNode())) if (ISD::isBuildVectorAllZeros(N0.getNode()))
// do not return N0, because undef node may exist in N0 // do not return N0, because undef node may exist in N0
return DAG.getConstant( return DAG.getConstant(APInt::getNullValue(N0.getScalarValueSizeInBits()),
APInt::getNullValue( SDLoc(N), N0.getValueType());
N0.getValueType().getScalarSizeInBits()),
SDLoc(N), N0.getValueType());
if (ISD::isBuildVectorAllZeros(N1.getNode())) if (ISD::isBuildVectorAllZeros(N1.getNode()))
// do not return N1, because undef node may exist in N1 // do not return N1, because undef node may exist in N1
return DAG.getConstant( return DAG.getConstant(APInt::getNullValue(N1.getScalarValueSizeInBits()),
APInt::getNullValue( SDLoc(N), N1.getValueType());
N1.getValueType().getScalarSizeInBits()),
SDLoc(N), N1.getValueType());
// fold (and x, -1) -> x, vector edition // fold (and x, -1) -> x, vector edition
if (ISD::isBuildVectorAllOnes(N0.getNode())) if (ISD::isBuildVectorAllOnes(N0.getNode()))
@ -3327,7 +3323,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
EVT MemVT = LN0->getMemoryVT(); EVT MemVT = LN0->getMemoryVT();
// If we zero all the possible extended bits, then we can turn this into // If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal. // a zextload if we are running before legalize or the operation is legal.
unsigned BitWidth = N1.getValueType().getScalarSizeInBits(); unsigned BitWidth = N1.getScalarValueSizeInBits();
if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
BitWidth - MemVT.getScalarSizeInBits())) && BitWidth - MemVT.getScalarSizeInBits())) &&
((!LegalOperations && !LN0->isVolatile()) || ((!LegalOperations && !LN0->isVolatile()) ||
@ -3347,7 +3343,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
EVT MemVT = LN0->getMemoryVT(); EVT MemVT = LN0->getMemoryVT();
// If we zero all the possible extended bits, then we can turn this into // If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal. // a zextload if we are running before legalize or the operation is legal.
unsigned BitWidth = N1.getValueType().getScalarSizeInBits(); unsigned BitWidth = N1.getScalarValueSizeInBits();
if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
BitWidth - MemVT.getScalarSizeInBits())) && BitWidth - MemVT.getScalarSizeInBits())) &&
((!LegalOperations && !LN0->isVolatile()) || ((!LegalOperations && !LN0->isVolatile()) ||
@ -3751,15 +3747,13 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
if (ISD::isBuildVectorAllOnes(N0.getNode())) if (ISD::isBuildVectorAllOnes(N0.getNode()))
// do not return N0, because undef node may exist in N0 // do not return N0, because undef node may exist in N0
return DAG.getConstant( return DAG.getConstant(
APInt::getAllOnesValue( APInt::getAllOnesValue(N0.getScalarValueSizeInBits()), SDLoc(N),
N0.getValueType().getScalarSizeInBits()), N0.getValueType());
SDLoc(N), N0.getValueType());
if (ISD::isBuildVectorAllOnes(N1.getNode())) if (ISD::isBuildVectorAllOnes(N1.getNode()))
// do not return N1, because undef node may exist in N1 // do not return N1, because undef node may exist in N1
return DAG.getConstant( return DAG.getConstant(
APInt::getAllOnesValue( APInt::getAllOnesValue(N1.getScalarValueSizeInBits()), SDLoc(N),
N1.getValueType().getScalarSizeInBits()), N1.getValueType());
SDLoc(N), N1.getValueType());
// fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask) // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask)
// Do this only if the resulting shuffle is legal. // Do this only if the resulting shuffle is legal.
@ -6102,8 +6096,8 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
// See if the value being truncated is already sign extended. If so, just // See if the value being truncated is already sign extended. If so, just
// eliminate the trunc/sext pair. // eliminate the trunc/sext pair.
SDValue Op = N0.getOperand(0); SDValue Op = N0.getOperand(0);
unsigned OpBits = Op.getValueType().getScalarSizeInBits(); unsigned OpBits = Op.getScalarValueSizeInBits();
unsigned MidBits = N0.getValueType().getScalarSizeInBits(); unsigned MidBits = N0.getScalarValueSizeInBits();
unsigned DestBits = VT.getScalarSizeInBits(); unsigned DestBits = VT.getScalarSizeInBits();
unsigned NumSignBits = DAG.ComputeNumSignBits(Op); unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
@ -6265,7 +6259,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
// sext(setcc x, y, cc) -> (select (setcc x, y, cc), T, 0) // sext(setcc x, y, cc) -> (select (setcc x, y, cc), T, 0)
// Here, T can be 1 or -1, depending on the type of the setcc and // Here, T can be 1 or -1, depending on the type of the setcc and
// getBooleanContents(). // getBooleanContents().
unsigned SetCCWidth = N0.getValueType().getScalarSizeInBits(); unsigned SetCCWidth = N0.getScalarValueSizeInBits();
SDLoc DL(N); SDLoc DL(N);
// To determine the "true" side of the select, we need to know the high bit // To determine the "true" side of the select, we need to know the high bit
@ -7041,7 +7035,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
// if x is small enough. // if x is small enough.
if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
SDValue N00 = N0.getOperand(0); SDValue N00 = N0.getOperand(0);
if (N00.getValueType().getScalarSizeInBits() <= EVTBits && if (N00.getScalarValueSizeInBits() <= EVTBits &&
(!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00, N1); return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00, N1);
} }
@ -9391,7 +9385,7 @@ SDValue DAGCombiner::visitFNEG(SDNode *N) {
if (N0.getValueType().isVector()) { if (N0.getValueType().isVector()) {
// For a vector, get a mask such as 0x80... per scalar element // For a vector, get a mask such as 0x80... per scalar element
// and splat it. // and splat it.
SignMask = APInt::getSignBit(N0.getValueType().getScalarSizeInBits()); SignMask = APInt::getSignBit(N0.getScalarValueSizeInBits());
SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask); SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
} else { } else {
// For a scalar, just generate 0x80... // For a scalar, just generate 0x80...
@ -9496,7 +9490,7 @@ SDValue DAGCombiner::visitFABS(SDNode *N) {
if (N0.getValueType().isVector()) { if (N0.getValueType().isVector()) {
// For a vector, get a mask such as 0x7f... per scalar element // For a vector, get a mask such as 0x7f... per scalar element
// and splat it. // and splat it.
SignMask = ~APInt::getSignBit(N0.getValueType().getScalarSizeInBits()); SignMask = ~APInt::getSignBit(N0.getScalarValueSizeInBits());
SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask); SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
} else { } else {
// For a scalar, just generate 0x7f... // For a scalar, just generate 0x7f...
@ -12159,11 +12153,9 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
// See if we can simplify the input to this truncstore with knowledge that // See if we can simplify the input to this truncstore with knowledge that
// only the low bits are being used. For example: // only the low bits are being used. For example:
// "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
SDValue Shorter = SDValue Shorter = GetDemandedBits(
GetDemandedBits(Value, Value, APInt::getLowBitsSet(Value.getScalarValueSizeInBits(),
APInt::getLowBitsSet( ST->getMemoryVT().getScalarSizeInBits()));
Value.getValueType().getScalarSizeInBits(),
ST->getMemoryVT().getScalarSizeInBits()));
AddToWorklist(Value.getNode()); AddToWorklist(Value.getNode());
if (Shorter.getNode()) if (Shorter.getNode())
return DAG.getTruncStore(Chain, SDLoc(N), Shorter, return DAG.getTruncStore(Chain, SDLoc(N), Shorter,
@ -12171,10 +12163,10 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
// Otherwise, see if we can simplify the operation with // Otherwise, see if we can simplify the operation with
// SimplifyDemandedBits, which only works if the value has a single use. // SimplifyDemandedBits, which only works if the value has a single use.
if (SimplifyDemandedBits(Value, if (SimplifyDemandedBits(
APInt::getLowBitsSet( Value,
Value.getValueType().getScalarSizeInBits(), APInt::getLowBitsSet(Value.getScalarValueSizeInBits(),
ST->getMemoryVT().getScalarSizeInBits()))) ST->getMemoryVT().getScalarSizeInBits())))
return SDValue(N, 0); return SDValue(N, 0);
} }

12
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -1012,7 +1012,7 @@ SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) {
"getZeroExtendInReg should use the vector element type instead of " "getZeroExtendInReg should use the vector element type instead of "
"the vector type!"); "the vector type!");
if (Op.getValueType() == VT) return Op; if (Op.getValueType() == VT) return Op;
unsigned BitWidth = Op.getValueType().getScalarSizeInBits(); unsigned BitWidth = Op.getScalarValueSizeInBits();
APInt Imm = APInt::getLowBitsSet(BitWidth, APInt Imm = APInt::getLowBitsSet(BitWidth,
VT.getSizeInBits()); VT.getSizeInBits());
return getNode(ISD::AND, DL, Op.getValueType(), Op, return getNode(ISD::AND, DL, Op.getValueType(), Op,
@ -1984,7 +1984,7 @@ bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const {
if (Op.getValueType().isVector()) if (Op.getValueType().isVector())
return false; return false;
unsigned BitWidth = Op.getValueType().getScalarSizeInBits(); unsigned BitWidth = Op.getScalarValueSizeInBits();
return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth);
} }
@ -2002,7 +2002,7 @@ bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask,
/// them in the KnownZero/KnownOne bitsets. /// them in the KnownZero/KnownOne bitsets.
void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero, void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
APInt &KnownOne, unsigned Depth) const { APInt &KnownOne, unsigned Depth) const {
unsigned BitWidth = Op.getValueType().getScalarSizeInBits(); unsigned BitWidth = Op.getScalarValueSizeInBits();
KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
if (Depth == 6) if (Depth == 6)
@ -2549,14 +2549,12 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const {
} }
case ISD::SIGN_EXTEND: case ISD::SIGN_EXTEND:
Tmp = Tmp = VTBits - Op.getOperand(0).getScalarValueSizeInBits();
VTBits-Op.getOperand(0).getValueType().getScalarSizeInBits();
return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp;
case ISD::SIGN_EXTEND_INREG: case ISD::SIGN_EXTEND_INREG:
// Max of the input and what this extends. // Max of the input and what this extends.
Tmp = Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getScalarSizeInBits();
cast<VTSDNode>(Op.getOperand(1))->getVT().getScalarSizeInBits();
Tmp = VTBits-Tmp+1; Tmp = VTBits-Tmp+1;
Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1);

11
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -432,7 +432,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
TargetLoweringOpt &TLO, TargetLoweringOpt &TLO,
unsigned Depth) const { unsigned Depth) const {
unsigned BitWidth = DemandedMask.getBitWidth(); unsigned BitWidth = DemandedMask.getBitWidth();
assert(Op.getValueType().getScalarSizeInBits() == BitWidth && assert(Op.getScalarValueSizeInBits() == BitWidth &&
"Mask size mismatches value type size!"); "Mask size mismatches value type size!");
APInt NewMask = DemandedMask; APInt NewMask = DemandedMask;
SDLoc dl(Op); SDLoc dl(Op);
@ -984,8 +984,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
break; break;
} }
case ISD::ZERO_EXTEND: { case ISD::ZERO_EXTEND: {
unsigned OperandBitWidth = unsigned OperandBitWidth = Op.getOperand(0).getScalarValueSizeInBits();
Op.getOperand(0).getValueType().getScalarSizeInBits();
APInt InMask = NewMask.trunc(OperandBitWidth); APInt InMask = NewMask.trunc(OperandBitWidth);
// If none of the top bits are demanded, convert this into an any_extend. // If none of the top bits are demanded, convert this into an any_extend.
@ -1047,8 +1046,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
break; break;
} }
case ISD::ANY_EXTEND: { case ISD::ANY_EXTEND: {
unsigned OperandBitWidth = unsigned OperandBitWidth = Op.getOperand(0).getScalarValueSizeInBits();
Op.getOperand(0).getValueType().getScalarSizeInBits();
APInt InMask = NewMask.trunc(OperandBitWidth); APInt InMask = NewMask.trunc(OperandBitWidth);
if (SimplifyDemandedBits(Op.getOperand(0), InMask, if (SimplifyDemandedBits(Op.getOperand(0), InMask,
KnownZero, KnownOne, TLO, Depth+1)) KnownZero, KnownOne, TLO, Depth+1))
@ -1061,8 +1059,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
case ISD::TRUNCATE: { case ISD::TRUNCATE: {
// Simplify the input, using demanded bit information, and compute the known // Simplify the input, using demanded bit information, and compute the known
// zero/one bits live out. // zero/one bits live out.
unsigned OperandBitWidth = unsigned OperandBitWidth = Op.getOperand(0).getScalarValueSizeInBits();
Op.getOperand(0).getValueType().getScalarSizeInBits();
APInt TruncMask = NewMask.zext(OperandBitWidth); APInt TruncMask = NewMask.zext(OperandBitWidth);
if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
KnownZero, KnownOne, TLO, Depth+1)) KnownZero, KnownOne, TLO, Depth+1))

2
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
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@ -1931,7 +1931,7 @@ static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth) {
return; return;
// Initialize UsefulBits // Initialize UsefulBits
if (!Depth) { if (!Depth) {
unsigned Bitwidth = Op.getValueType().getScalarSizeInBits(); unsigned Bitwidth = Op.getScalarValueSizeInBits();
// At the beginning, assume every produced bits is useful // At the beginning, assume every produced bits is useful
UsefulBits = APInt(Bitwidth, 0); UsefulBits = APInt(Bitwidth, 0);
UsefulBits.flipAllBits(); UsefulBits.flipAllBits();

8
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -11022,11 +11022,9 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
int Bits = IID == Intrinsic::ppc_qpx_qvlpcld ? int Bits = IID == Intrinsic::ppc_qpx_qvlpcld ?
5 /* 32 byte alignment */ : 4 /* 16 byte alignment */; 5 /* 32 byte alignment */ : 4 /* 16 byte alignment */;
if (DAG.MaskedValueIsZero( if (DAG.MaskedValueIsZero(Add->getOperand(1),
Add->getOperand(1), APInt::getAllOnesValue(Bits /* alignment */)
APInt::getAllOnesValue(Bits /* alignment */) .zext(Add.getScalarValueSizeInBits()))) {
.zext(
Add.getValueType().getScalarSizeInBits()))) {
SDNode *BasePtr = Add->getOperand(0).getNode(); SDNode *BasePtr = Add->getOperand(0).getNode();
for (SDNode::use_iterator UI = BasePtr->use_begin(), for (SDNode::use_iterator UI = BasePtr->use_begin(),
UE = BasePtr->use_end(); UE = BasePtr->use_end();

2
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
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@ -1435,7 +1435,7 @@ bool X86DAGToDAGISel::selectVectorAddr(SDNode *Parent, SDValue N, SDValue &Base,
SDLoc DL(N); SDLoc DL(N);
Base = Mgs->getBasePtr(); Base = Mgs->getBasePtr();
Index = Mgs->getIndex(); Index = Mgs->getIndex();
unsigned ScalarSize = Mgs->getValue().getValueType().getScalarSizeInBits(); unsigned ScalarSize = Mgs->getValue().getScalarValueSizeInBits();
Scale = getI8Imm(ScalarSize/8, DL); Scale = getI8Imm(ScalarSize/8, DL);
// If Base is 0, the whole address is in index and the Scale is 1 // If Base is 0, the whole address is in index and the Scale is 1

8
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -24782,7 +24782,7 @@ unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
unsigned Depth) const { unsigned Depth) const {
// SETCC_CARRY sets the dest to ~0 for true or 0 for false. // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
if (Op.getOpcode() == X86ISD::SETCC_CARRY) if (Op.getOpcode() == X86ISD::SETCC_CARRY)
return Op.getValueType().getScalarSizeInBits(); return Op.getScalarValueSizeInBits();
// Fallback case. // Fallback case.
return 1; return 1;
@ -27421,7 +27421,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
!DCI.isBeforeLegalize() && !DCI.isBeforeLegalize() &&
!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) { !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
unsigned BitWidth = Cond.getValueType().getScalarSizeInBits(); unsigned BitWidth = Cond.getScalarValueSizeInBits();
// Don't optimize vector selects that map to mask-registers. // Don't optimize vector selects that map to mask-registers.
if (BitWidth == 1) if (BitWidth == 1)
@ -28682,7 +28682,7 @@ static SDValue combineVectorZext(SDNode *N, SelectionDAG &DAG,
SplatBitSize, HasAnyUndefs)) SplatBitSize, HasAnyUndefs))
return SDValue(); return SDValue();
unsigned ResSize = N1.getValueType().getScalarSizeInBits(); unsigned ResSize = N1.getScalarValueSizeInBits();
// Make sure the splat matches the mask we expect // Make sure the splat matches the mask we expect
if (SplatBitSize > ResSize || if (SplatBitSize > ResSize ||
(SplatValue + 1).exactLogBase2() != (int)SrcSize) (SplatValue + 1).exactLogBase2() != (int)SrcSize)
@ -30356,7 +30356,7 @@ static SDValue isFNEG(SDNode *N) {
SDValue Op0 = peekThroughBitcasts(Op.getOperand(0)); SDValue Op0 = peekThroughBitcasts(Op.getOperand(0));
unsigned EltBits = Op1.getValueType().getScalarSizeInBits(); unsigned EltBits = Op1.getScalarValueSizeInBits();
auto isSignBitValue = [&](const ConstantFP *C) { auto isSignBitValue = [&](const ConstantFP *C) {
return C->getValueAPF().bitcastToAPInt() == APInt::getSignBit(EltBits); return C->getValueAPF().bitcastToAPInt() == APInt::getSignBit(EltBits);
}; };