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R600/SI: Add VI instructions 

llvm-svn: 223603
This commit is contained in:
Marek Olsak 2014-12-07 12:18:57 +00:00
parent b08604c4cd
commit 5df00d63e2
12 changed files with 1488 additions and 700 deletions
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5
llvm/lib/Target/R600/AMDGPU.td
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@ -147,6 +147,11 @@ def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
//===----------------------------------------------------------------------===//
def AMDGPUInstrInfo : InstrInfo {

2
llvm/lib/Target/R600/AMDGPUInstrInfo.cpp
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@ -342,7 +342,7 @@ int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const {
namespace llvm {
namespace AMDGPU {
int getMCOpcode(uint16_t Opcode, unsigned Gen) {
return getMCOpcode(Opcode);
return getMCOpcodeGen(Opcode, (enum Subtarget)Gen);
}
}
}

9
llvm/lib/Target/R600/AMDGPUMCInstLower.cpp
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@ -40,8 +40,13 @@ AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st):
{ }
enum AMDGPUMCInstLower::SISubtarget
AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned) const {
return AMDGPUMCInstLower::SI;
AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned Gen) const {
switch (Gen) {
default:
return AMDGPUMCInstLower::SI;
case AMDGPUSubtarget::VOLCANIC_ISLANDS:
return AMDGPUMCInstLower::VI;
}
}
unsigned AMDGPUMCInstLower::getMCOpcode(unsigned MIOpcode) const {

3
llvm/lib/Target/R600/AMDGPUMCInstLower.h
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@ -22,7 +22,8 @@ class AMDGPUMCInstLower {
// This must be kept in sync with the SISubtarget class in SIInstrInfo.td
enum SISubtarget {
SI = 0
SI = 0,
VI = 1
};
MCContext &Ctx;

3
llvm/lib/Target/R600/AMDGPUSubtarget.h
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@ -39,7 +39,8 @@ public:
EVERGREEN,
NORTHERN_ISLANDS,
SOUTHERN_ISLANDS,
SEA_ISLANDS
SEA_ISLANDS,
VOLCANIC_ISLANDS,
};
private:

42
llvm/lib/Target/R600/CIInstructions.td Normal file
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@ -0,0 +1,42 @@
//===-- CIInstructions.td - CI Instruction Defintions ---------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
// Instruction definitions for CI and newer.
//===----------------------------------------------------------------------===//
def isCIVI : Predicate <
"Subtarget.getGeneration() == AMDGPUSubtarget::SEA_ISLANDS || "
"Subtarget.getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS"
>;
//===----------------------------------------------------------------------===//
// VOP1 Instructions
//===----------------------------------------------------------------------===//
let SubtargetPredicate = isCIVI in {
defm V_TRUNC_F64 : VOP1Inst <vop1<0x17>, "v_trunc_f64",
VOP_F64_F64, ftrunc
>;
defm V_CEIL_F64 : VOP1Inst <vop1<0x18>, "v_ceil_f64",
VOP_F64_F64, fceil
>;
defm V_FLOOR_F64 : VOP1Inst <vop1<0x1A>, "v_floor_f64",
VOP_F64_F64, ffloor
>;
defm V_RNDNE_F64 : VOP1Inst <vop1<0x19>, "v_rndne_f64",
VOP_F64_F64, frint
>;
defm V_LOG_LEGACY_F32 : VOP1Inst <vop1<0x45, 0x4c>, "v_log_legacy_f32",
VOP_F32_F32
>;
defm V_EXP_LEGACY_F32 : VOP1Inst <vop1<0x46, 0x4b>, "v_exp_legacy_f32",
VOP_F32_F32
>;
} // End SubtargetPredicate = isCIVI

6
llvm/lib/Target/R600/Processors.td
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@ -108,3 +108,9 @@ def : Proc<"kaveri", SI_Itin, [FeatureSeaIslands]>;
def : Proc<"hawaii", SI_Itin, [FeatureSeaIslands]>;
def : Proc<"mullins", SI_Itin, [FeatureSeaIslands]>;
def : Proc<"tonga", SI_Itin, [FeatureVolcanicIslands]>;
def : Proc<"iceland", SI_Itin, [FeatureVolcanicIslands]>;
def : Proc<"carrizo", SI_Itin, [FeatureVolcanicIslands]>;

82
llvm/lib/Target/R600/SIInstrFormats.td
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@ -82,6 +82,21 @@ class Enc64 {
int Size = 8;
}
let Uses = [EXEC] in {
class VOPCCommon <dag ins, string asm, list<dag> pattern> :
InstSI <(outs VCCReg:$dst), ins, asm, pattern> {
let DisableEncoding = "$dst";
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let UseNamedOperandTable = 1;
let VOPC = 1;
let VALU = 1;
let Size = 4;
}
class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins, asm, pattern> {
let mayLoad = 0;
@ -90,6 +105,19 @@ class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> :
let UseNamedOperandTable = 1;
let VOP1 = 1;
let VALU = 1;
let Size = 4;
}
class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins, asm, pattern> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let UseNamedOperandTable = 1;
let VOP2 = 1;
let VALU = 1;
let Size = 4;
}
class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
@ -109,9 +137,10 @@ class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
let VALU = 1;
int Size = 8;
let Uses = [EXEC];
}
} // End Uses = [EXEC]
//===----------------------------------------------------------------------===//
// Scalar operations
//===----------------------------------------------------------------------===//
@ -185,8 +214,8 @@ class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
let Inst{31-27} = 0x18; //encoding
}
class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
InstSI<outs, ins, asm, pattern>, SOP1e <op> {
class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
InstSI<outs, ins, asm, pattern> {
let mayLoad = 0;
let mayStore = 0;
@ -195,8 +224,8 @@ class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
let SOP1 = 1;
}
class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins, asm, pattern>, SOP2e<op> {
class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins, asm, pattern> {
let mayLoad = 0;
let mayStore = 0;
@ -220,8 +249,8 @@ class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
let UseNamedOperandTable = 1;
}
class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins , asm, pattern>, SOPKe<op> {
class SOPK <dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins , asm, pattern> {
let mayLoad = 0;
let mayStore = 0;
@ -529,36 +558,16 @@ class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
VOP1e<op>;
class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins, asm, pattern>, VOP2e<op> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let UseNamedOperandTable = 1;
let VOP2 = 1;
let VALU = 1;
}
class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
VOP3Common <outs, ins, asm, pattern>, VOP3e<op>;
VOP2Common <outs, ins, asm, pattern>, VOP2e<op>;
class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
VOP3Common <outs, ins, asm, pattern>, VOP3be<op>;
class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
InstSI <(outs VCCReg:$dst), ins, asm, pattern>, VOPCe <op> {
VOPCCommon <ins, asm, pattern>, VOPCe <op>;
let DisableEncoding = "$dst";
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let UseNamedOperandTable = 1;
let VOPC = 1;
let VALU = 1;
}
class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins, asm, pattern>, VINTRPe<op> {
class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins, asm, pattern> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
@ -572,8 +581,8 @@ class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
let Uses = [EXEC] in {
class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins, asm, pattern> , DSe<op> {
class DS <dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins, asm, pattern> {
let LGKM_CNT = 1;
let DS = 1;
@ -581,8 +590,11 @@ class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
let DisableEncoding = "$m0";
}
class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
InstSI<outs, ins, asm, pattern>, MUBUFe <op> {
class DS_si <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
DS <outs, ins, asm, pattern>, DSe<op>;
class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
InstSI<outs, ins, asm, pattern> {
let VM_CNT = 1;
let EXP_CNT = 1;

752
llvm/lib/Target/R600/SIInstrInfo.td
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File diff suppressed because it is too large Load Diff

1056
llvm/lib/Target/R600/SIInstructions.td
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File diff suppressed because it is too large Load Diff

145
llvm/lib/Target/R600/VIInstrFormats.td Normal file
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@ -0,0 +1,145 @@
//===-- VIInstrFormats.td - VI Instruction Encodings ----------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// VI Instruction format definitions.
//
//===----------------------------------------------------------------------===//
class DSe_vi <bits<8> op> : Enc64 {
bits<8> vdst;
bits<1> gds;
bits<8> addr;
bits<8> data0;
bits<8> data1;
bits<8> offset0;
bits<8> offset1;
let Inst{7-0} = offset0;
let Inst{15-8} = offset1;
let Inst{16} = gds;
let Inst{24-17} = op;
let Inst{31-26} = 0x36; //encoding
let Inst{39-32} = addr;
let Inst{47-40} = data0;
let Inst{55-48} = data1;
let Inst{63-56} = vdst;
}
class MUBUFe_vi <bits<7> op> : Enc64 {
bits<12> offset;
bits<1> offen;
bits<1> idxen;
bits<1> glc;
bits<1> lds;
bits<8> vaddr;
bits<8> vdata;
bits<7> srsrc;
bits<1> slc;
bits<1> tfe;
bits<8> soffset;
let Inst{11-0} = offset;
let Inst{12} = offen;
let Inst{13} = idxen;
let Inst{14} = glc;
let Inst{16} = lds;
let Inst{17} = slc;
let Inst{24-18} = op;
let Inst{31-26} = 0x38; //encoding
let Inst{39-32} = vaddr;
let Inst{47-40} = vdata;
let Inst{52-48} = srsrc{6-2};
let Inst{55} = tfe;
let Inst{63-56} = soffset;
}
class MTBUFe_vi <bits<4> op> : Enc64 {
bits<12> offset;
bits<1> offen;
bits<1> idxen;
bits<1> glc;
bits<4> dfmt;
bits<3> nfmt;
bits<8> vaddr;
bits<8> vdata;
bits<7> srsrc;
bits<1> slc;
bits<1> tfe;
bits<8> soffset;
let Inst{11-0} = offset;
let Inst{12} = offen;
let Inst{13} = idxen;
let Inst{14} = glc;
let Inst{18-15} = op;
let Inst{22-19} = dfmt;
let Inst{25-23} = nfmt;
let Inst{31-26} = 0x3a; //encoding
let Inst{39-32} = vaddr;
let Inst{47-40} = vdata;
let Inst{52-48} = srsrc{6-2};
let Inst{54} = slc;
let Inst{55} = tfe;
let Inst{63-56} = soffset;
}
class SMEMe_vi <bits<8> op, bit imm> : Enc64 {
bits<7> sbase;
bits<7> sdata;
bits<1> glc;
bits<20> offset;
let Inst{5-0} = sbase{6-1};
let Inst{12-6} = sdata;
let Inst{16} = glc;
let Inst{17} = imm;
let Inst{25-18} = op;
let Inst{31-26} = 0x30; //encoding
let Inst{51-32} = offset;
}
class VOP3e_vi <bits<10> op> : Enc64 {
bits<8> dst;
bits<2> src0_modifiers;
bits<9> src0;
bits<2> src1_modifiers;
bits<9> src1;
bits<2> src2_modifiers;
bits<9> src2;
bits<1> clamp;
bits<2> omod;
let Inst{7-0} = dst;
let Inst{8} = src0_modifiers{1};
let Inst{9} = src1_modifiers{1};
let Inst{10} = src2_modifiers{1};
let Inst{15} = clamp;
let Inst{25-16} = op;
let Inst{31-26} = 0x34; //encoding
let Inst{40-32} = src0;
let Inst{49-41} = src1;
let Inst{58-50} = src2;
let Inst{60-59} = omod;
let Inst{61} = src0_modifiers{0};
let Inst{62} = src1_modifiers{0};
let Inst{63} = src2_modifiers{0};
}
class EXPe_vi : EXPe {
let Inst{31-26} = 0x31; //encoding
}
class VINTRPe_vi <bits<2> op> : VINTRPe <op> {
let Inst{31-26} = 0x35; // encoding
}

83
llvm/lib/Target/R600/VIInstructions.td Normal file
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@ -0,0 +1,83 @@
//===-- VIInstructions.td - VI Instruction Defintions ---------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
// Instruction definitions for VI and newer.
//===----------------------------------------------------------------------===//
def isVI : Predicate <
"Subtarget.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS"
>;
let SubtargetPredicate = isVI in {
def V_LDEXP_F32 : VOP3InstVI <0x288, "v_ldexp_f32", VOP_F32_F32_I32,
AMDGPUldexp
>;
def V_BFM_B32 : VOP3InstVI <0x293, "v_bfm_b32", VOP_I32_I32_I32, AMDGPUbfm>;
def V_BCNT_U32_B32 : VOP3InstVI <0x28b, "v_bcnt_u32_b32", VOP_I32_I32_I32>;
def V_MBCNT_LO_U32_B32 : VOP3InstVI <0x28c, "v_mbcnt_lo_u32_b32",
VOP_I32_I32_I32
>;
def V_MBCNT_HI_U32_B32 : VOP3InstVI <0x28d, "v_mbcnt_hi_u32_b32",
VOP_I32_I32_I32
>;
def V_CVT_PKRTZ_F16_F32 : VOP3InstVI <0x296, "v_cvt_pkrtz_f16_f32",
VOP_I32_F32_F32, int_SI_packf16
>;
defm BUFFER_LOAD_DWORD_VI : MUBUF_Load_Helper_vi <
0x14, "buffer_load_dword", VReg_32, i32, global_load
>;
defm BUFFER_LOAD_FORMAT_XYZW_VI : MUBUF_Load_Helper_vi <
0x03, "buffer_load_format_xyzw", VReg_128
>;
} // End SubtargetPredicate = isVI
//===----------------------------------------------------------------------===//
// VOP2 Patterns
//===----------------------------------------------------------------------===//
let Predicates = [isVI] in {
def : Pat <
(int_SI_tid),
(V_MBCNT_HI_U32_B32 0xffffffff,
(V_MBCNT_LO_U32_B32 0xffffffff, 0))
>;
//===----------------------------------------------------------------------===//
// MUBUF Patterns
//===----------------------------------------------------------------------===//
// Offset in an 32Bit VGPR
def : Pat <
(SIload_constant v4i32:$sbase, i32:$voff),
(BUFFER_LOAD_DWORD_VI_OFFEN $sbase, $voff, 0, 0, 0, 0, 0)
>;
// Offset in an 32Bit VGPR
def : Pat <
(SIload_constant v4i32:$sbase, i32:$voff),
(BUFFER_LOAD_DWORD_VI_OFFEN $sbase, $voff, 0, 0, 0, 0, 0)
>;
/* int_SI_vs_load_input */
def : Pat<
(SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr),
(BUFFER_LOAD_FORMAT_XYZW_VI_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
>;
defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_VI_OFFSET,
BUFFER_LOAD_DWORD_VI_OFFEN,
BUFFER_LOAD_DWORD_VI_IDXEN,
BUFFER_LOAD_DWORD_VI_BOTHEN>;
} // End Predicates = [isVI]