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Enable support for returning i1, i8, and i16. Nothing special todo as it's the 

callee's responsibility to sign or zero-extend the return value.  The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).

llvm-svn: 144047
This commit is contained in:
Chad Rosier 2011-11-08 00:03:32 +00:00
parent 2dc40434aa
commit 5de1bea5c9
3 changed files with 24 additions and 1 deletions
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2
llvm/lib/Target/ARM/ARMCallingConv.td
View File

@ -43,6 +43,7 @@ def CC_ARM_APCS : CallingConv<[
]>;
def RetCC_ARM_APCS : CallingConv<[
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
CCIfType<[f32], CCBitConvertToType<i32>>,
// Handle all vector types as either f64 or v2f64.
@ -106,6 +107,7 @@ def CC_ARM_AAPCS_Common : CallingConv<[
]>;
def RetCC_ARM_AAPCS_Common : CallingConv<[
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
]>;

8
llvm/lib/Target/ARM/ARMFastISel.cpp
View File

@ -1697,6 +1697,11 @@ bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
} else {
assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
EVT CopyVT = RVLocs[0].getValVT();
// Special handling for extended integers.
if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
CopyVT = MVT::i32;
TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
unsigned ResultReg = createResultReg(DstRC);
@ -1913,7 +1918,8 @@ bool ARMFastISel::SelectCall(const Instruction *I) {
MVT RetVT;
if (RetTy->isVoidTy())
RetVT = MVT::isVoid;
else if (!isTypeLegal(RetTy, RetVT))
else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
RetVT != MVT::i8 && RetVT != MVT::i1)
return false;
// TODO: For now if we have long calls specified we don't handle the call.

15
llvm/test/CodeGen/ARM/fast-isel-call.ll
View File

@ -65,3 +65,18 @@ define void @foo(i8 %a, i16 %b) nounwind {
%7 = call i32 @t4(i16 zeroext 65535)
ret void
}
define void @foo2() nounwind {
%1 = call signext i16 @t5()
%2 = call zeroext i16 @t6()
%3 = call signext i8 @t7()
%4 = call zeroext i8 @t8()
%5 = call zeroext i1 @t9()
ret void
}
declare signext i16 @t5();
declare zeroext i16 @t6();
declare signext i8 @t7();
declare zeroext i8 @t8();
declare zeroext i1 @t9();