parent
5dbfa76334
commit
5ddd564e19
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@ -858,7 +858,7 @@ bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) {
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const SIRegisterInfo *TRI = ST.getRegisterInfo();
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const MachineOperand *SDST = TII->getNamedOperand(*MI, SDSTName);
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if (!SDST) {
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for (auto MO : MI->implicit_operands()) {
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for (const auto &MO : MI->implicit_operands()) {
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if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg()))) {
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SDST = &MO;
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break;
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