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[ARM] Fix parsing of special register masks 

This parsing code was incorrectly checking for invalid characters, so an
invalid instruction like:
  msr spsr_w, r0
would be emitted as:
  msr spsr_cxsf, r0

Differential revision: https://reviews.llvm.org/D30462

llvm-svn: 296607
This commit is contained in:
Oliver Stannard 2017-03-01 10:51:04 +00:00
parent dfec81107f
commit 5d35b9e56c
2 changed files with 12 additions and 1 deletions
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2
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -4330,7 +4330,7 @@ ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
// If some specific flag is already set, it means that some letter is
// present more than once, this is not acceptable.
if (FlagsVal == ~0U || (FlagsVal & Flag))
if (Flag == ~0U || (FlagsVal & Flag))
return MatchOperand_NoMatch;
FlagsVal |= Flag;
}

11
llvm/test/MC/ARM/invalid-special-reg.s Normal file
View File

@ -0,0 +1,11 @@
@ RUN: not llvm-mc -triple armv7a--none-eabi < %s |& FileCheck %s
@ RUN: not llvm-mc -triple thumbv7a--none-eabi < %s |& FileCheck %s
msr apsr_c, r0
@ CHECK: invalid operand for instruction
msr cpsr_w
@ CHECK: invalid operand for instruction
msr cpsr_cc
@ CHECK: invalid operand for instruction
msr xpsr_c
@ CHECK: invalid operand for instruction