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[AArch64] Added vselect patterns with float and double types 

llvm-svn: 199925
This commit is contained in:
Ana Pazos 2014-01-23 19:18:57 +00:00
parent 4c96056acd
commit 5d31f6945b
2 changed files with 17 additions and 0 deletions
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4
llvm/lib/Target/AArch64/AArch64InstrNEON.td
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@ -473,6 +473,10 @@ multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
(INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
def : Pat<(v2i64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
(INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
def : Pat<(v2f64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
(INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
def : Pat<(v4f32 (opnode (v4i32 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
(INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
// Allow to match BSL instruction pattern with non-constant operand
def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),

13
llvm/test/CodeGen/AArch64/neon-bsl.ll
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@ -220,3 +220,16 @@ entry:
ret <2 x double> %vbsl3.i
}
define <2 x double> @test_bsl_v2f64(<2 x i1> %v1, <2 x double> %v2, <2 x double> %v3) {
; CHECK-LABEL: test_bsl_v2f64:
; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%1 = select <2 x i1> %v1, <2 x double> %v2, <2 x double> %v3
ret <2 x double> %1
}
define <4 x float> @test_bsl_v4f32(<4 x i1> %v1, <4 x float> %v2, <4 x float> %v3) {
; CHECK-LABEL: test_bsl_v4f32:
; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%1 = select <4 x i1> %v1, <4 x float> %v2, <4 x float> %v3
ret <4 x float> %1
}