[mips] Add support for isBranchOffsetInRange and use it for MipsLongBranch
Add support for this target hook, covering MIPS, microMIPS and MIPSR6, along with some tests. Also add missing getOppositeBranchOpc() cases exposed by the tests. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46794 llvm-svn: 332446
This commit is contained in:
Simon Dardis
parent
caa163ef6a
commit
5cf9de4b72
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@ -276,6 +276,163 @@ MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
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return BT_CondUncond;
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}
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bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const {
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switch (BranchOpc) {
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case Mips::B:
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case Mips::BAL:
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case Mips::BC1F:
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case Mips::BC1FL:
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case Mips::BC1T:
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case Mips::BC1TL:
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case Mips::BEQ: case Mips::BEQ64:
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case Mips::BEQL:
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case Mips::BGEZ: case Mips::BGEZ64:
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case Mips::BGEZL:
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case Mips::BGEZAL:
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case Mips::BGEZALL:
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case Mips::BGTZ: case Mips::BGTZ64:
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case Mips::BGTZL:
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case Mips::BLEZ: case Mips::BLEZ64:
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case Mips::BLEZL:
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case Mips::BLTZ: case Mips::BLTZ64:
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case Mips::BLTZL:
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case Mips::BLTZAL:
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case Mips::BLTZALL:
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case Mips::BNE: case Mips::BNE64:
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case Mips::BNEL:
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return isInt<18>(BrOffset);
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// microMIPSr3 branches
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case Mips::B_MM:
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case Mips::BC1F_MM:
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case Mips::BC1T_MM:
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case Mips::BEQ_MM:
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case Mips::BGEZ_MM:
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case Mips::BGEZAL_MM:
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case Mips::BGTZ_MM:
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case Mips::BLEZ_MM:
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case Mips::BLTZ_MM:
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case Mips::BLTZAL_MM:
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case Mips::BNE_MM:
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case Mips::BEQZC_MM:
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case Mips::BNEZC_MM:
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return isInt<17>(BrOffset);
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// microMIPSR3 short branches.
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case Mips::B16_MM:
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return isInt<11>(BrOffset);
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case Mips::BEQZ16_MM:
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case Mips::BNEZ16_MM:
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return isInt<8>(BrOffset);
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// MIPSR6 branches.
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case Mips::BALC:
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case Mips::BC:
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return isInt<28>(BrOffset);
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case Mips::BC1EQZ:
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case Mips::BC1NEZ:
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case Mips::BC2EQZ:
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case Mips::BC2NEZ:
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case Mips::BEQC: case Mips::BEQC64:
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case Mips::BNEC: case Mips::BNEC64:
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case Mips::BGEC: case Mips::BGEC64:
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case Mips::BGEUC: case Mips::BGEUC64:
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case Mips::BGEZC: case Mips::BGEZC64:
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case Mips::BGTZC: case Mips::BGTZC64:
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case Mips::BLEZC: case Mips::BLEZC64:
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case Mips::BLTC: case Mips::BLTC64:
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case Mips::BLTUC: case Mips::BLTUC64:
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case Mips::BLTZC: case Mips::BLTZC64:
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case Mips::BNVC:
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case Mips::BOVC:
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case Mips::BGEZALC:
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case Mips::BEQZALC:
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case Mips::BGTZALC:
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case Mips::BLEZALC:
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case Mips::BLTZALC:
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case Mips::BNEZALC:
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return isInt<18>(BrOffset);
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case Mips::BEQZC: case Mips::BEQZC64:
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case Mips::BNEZC: case Mips::BNEZC64:
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return isInt<23>(BrOffset);
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// microMIPSR6 branches
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case Mips::BC16_MMR6:
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return isInt<11>(BrOffset);
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case Mips::BEQZC16_MMR6:
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case Mips::BNEZC16_MMR6:
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return isInt<8>(BrOffset);
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case Mips::BALC_MMR6:
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case Mips::BC_MMR6:
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return isInt<27>(BrOffset);
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case Mips::BC1EQZC_MMR6:
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case Mips::BC1NEZC_MMR6:
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case Mips::BC2EQZC_MMR6:
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case Mips::BC2NEZC_MMR6:
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case Mips::BGEZALC_MMR6:
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case Mips::BEQZALC_MMR6:
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case Mips::BGTZALC_MMR6:
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case Mips::BLEZALC_MMR6:
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case Mips::BLTZALC_MMR6:
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case Mips::BNEZALC_MMR6:
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case Mips::BNVC_MMR6:
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case Mips::BOVC_MMR6:
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return isInt<17>(BrOffset);
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case Mips::BEQC_MMR6:
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case Mips::BNEC_MMR6:
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case Mips::BGEC_MMR6:
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case Mips::BGEUC_MMR6:
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case Mips::BGEZC_MMR6:
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case Mips::BGTZC_MMR6:
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case Mips::BLEZC_MMR6:
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case Mips::BLTC_MMR6:
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case Mips::BLTUC_MMR6:
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case Mips::BLTZC_MMR6:
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return isInt<18>(BrOffset);
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case Mips::BEQZC_MMR6:
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case Mips::BNEZC_MMR6:
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return isInt<23>(BrOffset);
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// DSP branches.
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case Mips::BPOSGE32:
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return isInt<18>(BrOffset);
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case Mips::BPOSGE32_MM:
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case Mips::BPOSGE32C_MMR3:
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return isInt<17>(BrOffset);
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// cnMIPS branches.
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case Mips::BBIT0:
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case Mips::BBIT032:
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case Mips::BBIT1:
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case Mips::BBIT132:
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return isInt<18>(BrOffset);
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// MSA branches.
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case Mips::BZ_B:
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case Mips::BZ_H:
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case Mips::BZ_W:
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case Mips::BZ_D:
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case Mips::BZ_V:
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case Mips::BNZ_B:
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case Mips::BNZ_H:
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case Mips::BNZ_W:
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case Mips::BNZ_D:
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case Mips::BNZ_V:
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return isInt<18>(BrOffset);
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}
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llvm_unreachable("Unknown branch instruction!");
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}
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/// Return the corresponding compact (no delay slot) form of a branch.
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unsigned MipsInstrInfo::getEquivalentCompactForm(
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const MachineBasicBlock::iterator I) const {
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@ -86,6 +86,10 @@ public:
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/// Determine the opcode of a non-delay slot form for a branch if one exists.
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unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const;
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/// Determine if the branch target is in range.
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bool isBranchOffsetInRange(unsigned BranchOpc,
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int64_t BrOffset) const override;
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/// Predicate to determine if an instruction can go in a forbidden slot.
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bool SafeInForbiddenSlot(const MachineInstr &MI) const;
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@ -584,8 +584,7 @@ bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
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if (!I->Br || I->HasLongBranch)
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continue;
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int ShVal = STI.inMicroMipsMode() ? 2 : 4;
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int64_t Offset = computeOffset(I->Br) / ShVal;
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int64_t Offset = computeOffset(I->Br);
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if (STI.isTargetNaCl()) {
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// The offset calculation does not include sandboxing instructions
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@ -595,8 +594,9 @@ bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
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Offset *= 2;
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}
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// Check if offset fits into 16-bit immediate field of branches.
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if (!ForceLongBranch && isInt<16>(Offset))
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// Check if offset fits into the immediate field of the branch.
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if (!ForceLongBranch &&
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TII->isBranchOffsetInRange(I->Br->getOpcode(), Offset))
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continue;
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I->HasLongBranch = true;
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@ -427,6 +427,10 @@ unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
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case Mips::BGEZ: return Mips::BLTZ;
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case Mips::BLTZ: return Mips::BGEZ;
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case Mips::BLEZ: return Mips::BGTZ;
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case Mips::BGTZ_MM: return Mips::BLEZ_MM;
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case Mips::BGEZ_MM: return Mips::BLTZ_MM;
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case Mips::BLTZ_MM: return Mips::BGEZ_MM;
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case Mips::BLEZ_MM: return Mips::BGTZ_MM;
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case Mips::BEQ64: return Mips::BNE64;
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case Mips::BNE64: return Mips::BEQ64;
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case Mips::BGTZ64: return Mips::BLEZ64;
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@ -435,24 +439,40 @@ unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
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case Mips::BLEZ64: return Mips::BGTZ64;
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case Mips::BC1T: return Mips::BC1F;
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case Mips::BC1F: return Mips::BC1T;
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case Mips::BEQZC_MM: return Mips::BNEZC_MM;
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case Mips::BNEZC_MM: return Mips::BEQZC_MM;
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case Mips::BC1T_MM: return Mips::BC1F_MM;
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case Mips::BC1F_MM: return Mips::BC1T_MM;
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case Mips::BEQZ16_MM: return Mips::BNEZ16_MM;
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case Mips::BNEZ16_MM: return Mips::BEQZ16_MM;
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case Mips::BEQZC_MM: return Mips::BNEZC_MM;
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case Mips::BNEZC_MM: return Mips::BEQZC_MM;
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case Mips::BEQZC: return Mips::BNEZC;
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case Mips::BNEZC: return Mips::BEQZC;
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case Mips::BLEZC: return Mips::BGTZC;
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case Mips::BGEZC: return Mips::BLTZC;
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case Mips::BGEC: return Mips::BLTC;
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case Mips::BGTZC: return Mips::BLEZC;
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case Mips::BLTZC: return Mips::BGEZC;
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case Mips::BLTC: return Mips::BGEC;
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case Mips::BGEUC: return Mips::BLTUC;
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case Mips::BLTUC: return Mips::BGEUC;
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case Mips::BEQC: return Mips::BNEC;
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case Mips::BNEC: return Mips::BEQC;
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case Mips::BGTZC: return Mips::BLEZC;
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case Mips::BGEZC: return Mips::BLTZC;
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case Mips::BLTZC: return Mips::BGEZC;
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case Mips::BLEZC: return Mips::BGTZC;
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case Mips::BC1EQZ: return Mips::BC1NEZ;
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case Mips::BC1NEZ: return Mips::BC1EQZ;
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case Mips::BEQZC_MMR6: return Mips::BNEZC_MMR6;
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case Mips::BNEZC_MMR6: return Mips::BEQZC_MMR6;
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case Mips::BLEZC_MMR6: return Mips::BGTZC_MMR6;
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case Mips::BGEZC_MMR6: return Mips::BLTZC_MMR6;
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case Mips::BGEC_MMR6: return Mips::BLTC_MMR6;
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case Mips::BGTZC_MMR6: return Mips::BLEZC_MMR6;
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case Mips::BLTZC_MMR6: return Mips::BGEZC_MMR6;
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case Mips::BLTC_MMR6: return Mips::BGEC_MMR6;
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case Mips::BGEUC_MMR6: return Mips::BLTUC_MMR6;
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case Mips::BLTUC_MMR6: return Mips::BGEUC_MMR6;
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case Mips::BEQC_MMR6: return Mips::BNEC_MMR6;
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case Mips::BNEC_MMR6: return Mips::BEQC_MMR6;
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case Mips::BGTZC_MMR6: return Mips::BLEZC_MMR6;
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case Mips::BGEZC_MMR6: return Mips::BLTZC_MMR6;
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case Mips::BLTZC_MMR6: return Mips::BGEZC_MMR6;
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case Mips::BLEZC_MMR6: return Mips::BGTZC_MMR6;
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case Mips::BC1EQZC_MMR6: return Mips::BC1NEZC_MMR6;
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case Mips::BC1NEZC_MMR6: return Mips::BC1EQZC_MMR6;
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case Mips::BEQZC64: return Mips::BNEZC64;
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case Mips::BNEZC64: return Mips::BEQZC64;
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case Mips::BEQC64: return Mips::BNEC64;
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@ -469,6 +489,16 @@ unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
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case Mips::BBIT1: return Mips::BBIT0;
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case Mips::BBIT032: return Mips::BBIT132;
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case Mips::BBIT132: return Mips::BBIT032;
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case Mips::BZ_B: return Mips::BNZ_B;
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case Mips::BZ_H: return Mips::BNZ_H;
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case Mips::BZ_W: return Mips::BNZ_W;
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case Mips::BZ_D: return Mips::BNZ_D;
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case Mips::BZ_V: return Mips::BNZ_V;
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case Mips::BNZ_B: return Mips::BZ_B;
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case Mips::BNZ_H: return Mips::BZ_H;
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case Mips::BNZ_W: return Mips::BZ_W;
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case Mips::BNZ_D: return Mips::BZ_D;
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case Mips::BNZ_V: return Mips::BZ_V;
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}
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}
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@ -0,0 +1,215 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=mips-mti-linux-gnu -mattr=+micromips %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch | FileCheck %s --check-prefix=MM
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# RUN: llc -mtriple=mips-mti-linux-gnu -mattr=+micromips %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch -relocation-model=pic | FileCheck %s --check-prefix=PIC
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# Test the long branch expansion of various branches
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--- |
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define i32 @a(double %a, double %b) {
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entry:
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%cmp = fcmp une double %a, %b
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br i1 %cmp, label %if.then, label %return
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if.then:
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call void asm sideeffect ".space 310680", "~{$1}"()
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ret i32 0
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return:
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ret i32 1
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}
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define i32 @b(double %a, double %b) {
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entry:
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%cmp = fcmp ueq double %a, %b
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br i1 %cmp, label %if.then, label %return
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if.then:
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call void asm sideeffect ".space 310680", "~{$1}"()
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ret i32 0
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return:
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ret i32 1
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}
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...
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---
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name: a
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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registers:
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liveins:
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- { reg: '$d6', virtual-reg: '' }
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- { reg: '$d7', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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; MM-LABEL: name: a
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; MM: bb.0.entry:
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; MM: successors: %bb.2(0x50000000), %bb.1(0x30000000)
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; MM: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
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; MM: BC1F_MM $fcc0, %bb.2, implicit-def $at {
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; MM: NOP
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; MM: }
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; MM: bb.1.entry:
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; MM: successors: %bb.3(0x80000000)
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; MM: J %bb.3, implicit-def $at {
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; MM: NOP
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; MM: }
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; MM: bb.2.if.then:
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; MM: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
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; MM: $v0 = LI16_MM 0
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; MM: JRC16_MM undef $ra, implicit killed $v0
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; MM: bb.3.return:
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; MM: $v0 = LI16_MM 1
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; MM: JRC16_MM undef $ra, implicit killed $v0
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; PIC-LABEL: name: a
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; PIC: bb.0.entry:
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; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
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; PIC: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
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; PIC: BC1F_MM $fcc0, %bb.3, implicit-def $at {
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; PIC: NOP
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; PIC: }
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; PIC: bb.1.entry:
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; PIC: successors: %bb.2(0x80000000)
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; PIC: $sp = ADDiu $sp, -8
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; PIC: SW $ra, $sp, 0
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; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
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; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
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; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
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; PIC: }
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; PIC: bb.2.entry:
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; PIC: successors: %bb.4(0x80000000)
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; PIC: $at = ADDu $ra, $at
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; PIC: $ra = LW $sp, 0
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; PIC: JR $at {
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; PIC: $sp = ADDiu $sp, 8
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; PIC: }
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; PIC: bb.3.if.then:
|
||||
; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
|
||||
; PIC: $v0 = LI16_MM 0
|
||||
; PIC: JRC16_MM undef $ra, implicit killed $v0
|
||||
; PIC: bb.4.return:
|
||||
; PIC: $v0 = LI16_MM 1
|
||||
; PIC: JRC16_MM undef $ra, implicit killed $v0
|
||||
bb.0.entry:
|
||||
successors: %bb.1(0x50000000), %bb.2(0x30000000)
|
||||
liveins: $d6, $d7
|
||||
|
||||
FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
|
||||
BC1T_MM killed $fcc0, %bb.2, implicit-def dead $at
|
||||
|
||||
bb.1.if.then:
|
||||
INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
|
||||
$v0 = LI16_MM 0
|
||||
PseudoReturn undef $ra, implicit killed $v0
|
||||
|
||||
bb.2.return:
|
||||
$v0 = LI16_MM 1
|
||||
PseudoReturn undef $ra, implicit killed $v0
|
||||
|
||||
...
|
||||
---
|
||||
name: b
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$d6', virtual-reg: '' }
|
||||
- { reg: '$d7', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MM-LABEL: name: b
|
||||
; MM: bb.0.entry:
|
||||
; MM: successors: %bb.2(0x30000000), %bb.1(0x50000000)
|
||||
; MM: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
|
||||
; MM: BC1F_MM killed $fcc0, %bb.1, implicit-def dead $at {
|
||||
; MM: NOP
|
||||
; MM: }
|
||||
; MM: bb.1.return:
|
||||
; MM: $v0 = LI16_MM 1
|
||||
; MM: JRC16_MM undef $ra, implicit killed $v0
|
||||
; MM: bb.2.if.then:
|
||||
; MM: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
|
||||
; MM: $v0 = LI16_MM 0
|
||||
; MM: JRC16_MM undef $ra, implicit killed $v0
|
||||
; PIC-LABEL: name: b
|
||||
; PIC: bb.0.entry:
|
||||
; PIC: successors: %bb.2(0x30000000), %bb.1(0x50000000)
|
||||
; PIC: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
|
||||
; PIC: BC1F_MM killed $fcc0, %bb.1, implicit-def dead $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1.return:
|
||||
; PIC: $v0 = LI16_MM 1
|
||||
; PIC: JRC16_MM undef $ra, implicit killed $v0
|
||||
; PIC: bb.2.if.then:
|
||||
; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
|
||||
; PIC: $v0 = LI16_MM 0
|
||||
; PIC: JRC16_MM undef $ra, implicit killed $v0
|
||||
bb.0.entry:
|
||||
successors: %bb.1(0x30000000), %bb.2(0x50000000)
|
||||
liveins: $d6, $d7
|
||||
|
||||
FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
|
||||
BC1F_MM killed $fcc0, %bb.2, implicit-def dead $at
|
||||
|
||||
bb.2.return:
|
||||
$v0 = LI16_MM 1
|
||||
PseudoReturn undef $ra, implicit killed $v0
|
||||
|
||||
bb.1.if.then:
|
||||
INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
|
||||
$v0 = LI16_MM 0
|
||||
PseudoReturn undef $ra, implicit killed $v0
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,219 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch | FileCheck %s --check-prefix=MM
|
||||
# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch -relocation-model=pic | FileCheck %s --check-prefix=PIC
|
||||
|
||||
# Test the long branch expansion of various branches
|
||||
|
||||
--- |
|
||||
|
||||
define i32 @a(double %a, double %b) {
|
||||
entry:
|
||||
%cmp = fcmp une double %a, %b
|
||||
br i1 %cmp, label %if.then, label %return
|
||||
|
||||
if.then:
|
||||
call void asm sideeffect ".space 810680", "~{$1}"()
|
||||
ret i32 0
|
||||
|
||||
return:
|
||||
ret i32 1
|
||||
}
|
||||
|
||||
define i32 @b(double %a, double %b) {
|
||||
entry:
|
||||
%cmp = fcmp ueq double %a, %b
|
||||
br i1 %cmp, label %if.then, label %return
|
||||
|
||||
if.then:
|
||||
call void asm sideeffect ".space 810680", "~{$1}"()
|
||||
ret i32 0
|
||||
|
||||
return:
|
||||
ret i32 1
|
||||
}
|
||||
|
||||
...
|
||||
---
|
||||
name: a
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$d12_64', virtual-reg: '' }
|
||||
- { reg: '$d14_64', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MM-LABEL: name: a
|
||||
; MM: bb.0.entry:
|
||||
; MM: successors: %bb.2(0x50000000), %bb.1(0x30000000)
|
||||
; MM: $f0 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64
|
||||
; MM: BC1EQZC_MMR6 $d0_64, %bb.2, implicit-def $at
|
||||
; MM: bb.1.entry:
|
||||
; MM: successors: %bb.3(0x80000000)
|
||||
; MM: BC_MMR6 %bb.3
|
||||
; MM: bb.2.if.then:
|
||||
; MM: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
|
||||
; MM: $v0 = LI16_MM 0
|
||||
; MM: JRC16_MM undef $ra, implicit $v0
|
||||
; MM: bb.3.return:
|
||||
; MM: $v0 = LI16_MM 1
|
||||
; MM: JRC16_MM undef $ra, implicit $v0
|
||||
; PIC-LABEL: name: a
|
||||
; PIC: bb.0.entry:
|
||||
; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
|
||||
; PIC: $f0 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64
|
||||
; PIC: BC1EQZC_MMR6 $d0_64, %bb.3, implicit-def $at
|
||||
; PIC: bb.1.entry:
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: BALC_MMR6 %bb.2, implicit-def $ra
|
||||
; PIC: bb.2.entry:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: JIC_MMR6 $at, 0, implicit-def $at
|
||||
; PIC: bb.3.if.then:
|
||||
; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
|
||||
; PIC: $v0 = LI16_MM 0
|
||||
; PIC: JRC16_MM undef $ra, implicit $v0
|
||||
; PIC: bb.4.return:
|
||||
; PIC: $v0 = LI16_MM 1
|
||||
; PIC: JRC16_MM undef $ra, implicit $v0
|
||||
bb.0.entry:
|
||||
successors: %bb.1(0x50000000), %bb.2(0x30000000)
|
||||
liveins: $d12_64, $d14_64
|
||||
|
||||
$f0 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64
|
||||
BC1NEZC_MMR6 killed $d0_64, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.if.then:
|
||||
INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
|
||||
$v0 = LI16_MM 0
|
||||
PseudoReturn undef $ra, implicit $v0
|
||||
|
||||
bb.2.return:
|
||||
$v0 = LI16_MM 1
|
||||
PseudoReturn undef $ra, implicit $v0
|
||||
|
||||
...
|
||||
---
|
||||
name: b
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$d12_64', virtual-reg: '' }
|
||||
- { reg: '$d14_64', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MM-LABEL: name: b
|
||||
; MM: bb.0.entry:
|
||||
; MM: successors: %bb.2(0x30000000), %bb.1(0x50000000)
|
||||
; MM: $f0 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64
|
||||
; MM: BC1NEZC_MMR6 $d0_64, %bb.2, implicit-def $at
|
||||
; MM: bb.1.entry:
|
||||
; MM: successors: %bb.3(0x80000000)
|
||||
; MM: BC_MMR6 %bb.3
|
||||
; MM: bb.2.if.then:
|
||||
; MM: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
|
||||
; MM: $v0 = LI16_MM 0
|
||||
; MM: JRC16_MM undef $ra, implicit $v0
|
||||
; MM: bb.3.return:
|
||||
; MM: $v0 = LI16_MM 1
|
||||
; MM: JRC16_MM undef $ra, implicit $v0
|
||||
; PIC-LABEL: name: b
|
||||
; PIC: bb.0.entry:
|
||||
; PIC: successors: %bb.3(0x30000000), %bb.1(0x50000000)
|
||||
; PIC: $f0 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64
|
||||
; PIC: BC1NEZC_MMR6 $d0_64, %bb.3, implicit-def $at
|
||||
; PIC: bb.1.entry:
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: BALC_MMR6 %bb.2, implicit-def $ra
|
||||
; PIC: bb.2.entry:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: JIC_MMR6 $at, 0, implicit-def $at
|
||||
; PIC: bb.3.if.then:
|
||||
; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
|
||||
; PIC: $v0 = LI16_MM 0
|
||||
; PIC: JRC16_MM undef $ra, implicit $v0
|
||||
; PIC: bb.4.return:
|
||||
; PIC: $v0 = LI16_MM 1
|
||||
; PIC: JRC16_MM undef $ra, implicit $v0
|
||||
bb.0.entry:
|
||||
successors: %bb.1(0x30000000), %bb.2(0x50000000)
|
||||
liveins: $d12_64, $d14_64
|
||||
|
||||
$f0 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64
|
||||
BC1EQZC_MMR6 killed $d0_64, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.if.then:
|
||||
INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
|
||||
$v0 = LI16_MM 0
|
||||
PseudoReturn undef $ra, implicit $v0
|
||||
|
||||
bb.2.return:
|
||||
$v0 = LI16_MM 1
|
||||
PseudoReturn undef $ra, implicit $v0
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,242 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=mips-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch | FileCheck %s --check-prefix=MIPS
|
||||
# RUN: llc -mtriple=mips-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch -relocation-model=pic | FileCheck %s --check-prefix=PIC
|
||||
# Test the long branch expansion of various branches
|
||||
|
||||
--- |
|
||||
|
||||
define i32 @a(double %a, double %b) {
|
||||
entry:
|
||||
%cmp = fcmp une double %a, %b
|
||||
br i1 %cmp, label %if.then, label %return
|
||||
|
||||
if.then:
|
||||
call void asm sideeffect ".space 310680", "~{$1}"()
|
||||
ret i32 0
|
||||
|
||||
return:
|
||||
ret i32 1
|
||||
}
|
||||
|
||||
define i32 @b(double %a, double %b) {
|
||||
entry:
|
||||
%cmp = fcmp une double %a, %b
|
||||
br i1 %cmp, label %if.then, label %return
|
||||
|
||||
if.then:
|
||||
call void asm sideeffect ".space 310680", "~{$1}"()
|
||||
ret i32 0
|
||||
|
||||
return:
|
||||
ret i32 1
|
||||
}
|
||||
|
||||
...
|
||||
---
|
||||
name: a
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$d6', virtual-reg: '' }
|
||||
- { reg: '$d7', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MIPS-LABEL: name: a
|
||||
; MIPS: bb.0.entry:
|
||||
; MIPS: successors: %bb.2(0x50000000), %bb.1(0x30000000)
|
||||
; MIPS: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
|
||||
; MIPS: BC1F $fcc0, %bb.2, implicit-def $at {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; MIPS: bb.1.entry:
|
||||
; MIPS: successors: %bb.3(0x80000000)
|
||||
; MIPS: J %bb.3, implicit-def $at {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; MIPS: bb.2.if.then:
|
||||
; MIPS: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
|
||||
; MIPS: PseudoReturn undef $ra, implicit killed $v0 {
|
||||
; MIPS: $v0 = ADDiu $zero, 0
|
||||
; MIPS: }
|
||||
; MIPS: bb.3.return:
|
||||
; MIPS: PseudoReturn undef $ra, implicit killed $v0 {
|
||||
; MIPS: $v0 = ADDiu $zero, 1
|
||||
; MIPS: }
|
||||
; PIC-LABEL: name: a
|
||||
; PIC: bb.0.entry:
|
||||
; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
|
||||
; PIC: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
|
||||
; PIC: BC1F $fcc0, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1.entry:
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: BAL_BR %bb.2, implicit-def $ra {
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2.entry:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: JR $at {
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: }
|
||||
; PIC: bb.3.if.then:
|
||||
; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
|
||||
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
|
||||
; PIC: $v0 = ADDiu $zero, 0
|
||||
; PIC: }
|
||||
; PIC: bb.4.return:
|
||||
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
|
||||
; PIC: $v0 = ADDiu $zero, 1
|
||||
; PIC: }
|
||||
bb.0.entry:
|
||||
successors: %bb.1(0x50000000), %bb.2(0x30000000)
|
||||
liveins: $d6, $d7
|
||||
|
||||
FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
|
||||
BC1T killed $fcc0, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.if.then:
|
||||
INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
|
||||
$v0 = ADDiu $zero, 0
|
||||
PseudoReturn undef $ra, implicit killed $v0
|
||||
|
||||
bb.2.return:
|
||||
$v0 = ADDiu $zero, 1
|
||||
PseudoReturn undef $ra, implicit killed $v0
|
||||
|
||||
...
|
||||
---
|
||||
name: b
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$d6', virtual-reg: '' }
|
||||
- { reg: '$d7', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MIPS-LABEL: name: b
|
||||
; MIPS: bb.0.entry:
|
||||
; MIPS: successors: %bb.2(0x50000000), %bb.1(0x30000000)
|
||||
; MIPS: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
|
||||
; MIPS: BC1T $fcc0, %bb.2, implicit-def $at {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; MIPS: bb.1.entry:
|
||||
; MIPS: successors: %bb.3(0x80000000)
|
||||
; MIPS: J %bb.3, implicit-def $at {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; MIPS: bb.2.if.then:
|
||||
; MIPS: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
|
||||
; MIPS: PseudoReturn undef $ra, implicit killed $v0 {
|
||||
; MIPS: $v0 = ADDiu $zero, 0
|
||||
; MIPS: }
|
||||
; MIPS: bb.3.return:
|
||||
; MIPS: PseudoReturn undef $ra, implicit killed $v0 {
|
||||
; MIPS: $v0 = ADDiu $zero, 1
|
||||
; MIPS: }
|
||||
; PIC-LABEL: name: b
|
||||
; PIC: bb.0.entry:
|
||||
; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
|
||||
; PIC: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
|
||||
; PIC: BC1T $fcc0, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1.entry:
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: BAL_BR %bb.2, implicit-def $ra {
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2.entry:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: JR $at {
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: }
|
||||
; PIC: bb.3.if.then:
|
||||
; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
|
||||
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
|
||||
; PIC: $v0 = ADDiu $zero, 0
|
||||
; PIC: }
|
||||
; PIC: bb.4.return:
|
||||
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
|
||||
; PIC: $v0 = ADDiu $zero, 1
|
||||
; PIC: }
|
||||
bb.0.entry:
|
||||
successors: %bb.1(0x50000000), %bb.2(0x30000000)
|
||||
liveins: $d6, $d7
|
||||
|
||||
FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
|
||||
BC1F killed $fcc0, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.if.then:
|
||||
INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
|
||||
$v0 = ADDiu $zero, 0
|
||||
PseudoReturn undef $ra, implicit killed $v0
|
||||
|
||||
bb.2.return:
|
||||
$v0 = ADDiu $zero, 1
|
||||
PseudoReturn undef $ra, implicit killed $v0
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,236 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch | FileCheck %s --check-prefix=R6
|
||||
# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch -relocation-model=pic | FileCheck %s --check-prefix=PIC
|
||||
|
||||
# Test the long branch expansion of various branches
|
||||
|
||||
--- |
|
||||
|
||||
define i32 @a(double %a, double %b) {
|
||||
entry:
|
||||
%cmp = fcmp une double %a, %b
|
||||
br i1 %cmp, label %if.then, label %return
|
||||
|
||||
if.then: ; preds = %entry
|
||||
call void asm sideeffect ".space 310680", "~{$1}"()
|
||||
ret i32 0
|
||||
|
||||
return: ; preds = %entry
|
||||
ret i32 1
|
||||
}
|
||||
|
||||
define i32 @b(double %a, double %b) {
|
||||
entry:
|
||||
%cmp = fcmp ueq double %a, %b
|
||||
br i1 %cmp, label %if.then, label %return
|
||||
|
||||
if.then: ; preds = %entry
|
||||
call void asm sideeffect ".space 310680", "~{$1}"()
|
||||
ret i32 0
|
||||
|
||||
return: ; preds = %entry
|
||||
ret i32 1
|
||||
}
|
||||
|
||||
|
||||
...
|
||||
---
|
||||
name: a
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$d12_64', virtual-reg: '' }
|
||||
- { reg: '$d14_64', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; R6-LABEL: name: a
|
||||
; R6: bb.0.entry:
|
||||
; R6: successors: %bb.2(0x50000000), %bb.1(0x30000000)
|
||||
; R6: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
|
||||
; R6: BC1NEZ $d0_64, %bb.2 {
|
||||
; R6: NOP
|
||||
; R6: }
|
||||
; R6: bb.1.entry:
|
||||
; R6: successors: %bb.3(0x80000000)
|
||||
; R6: BC %bb.3
|
||||
; R6: bb.2.if.then:
|
||||
; R6: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
|
||||
; R6: PseudoReturn undef $ra, implicit killed $v0 {
|
||||
; R6: $v0 = ADDiu $zero, 0
|
||||
; R6: }
|
||||
; R6: bb.3.return:
|
||||
; R6: PseudoReturn undef $ra, implicit killed $v0 {
|
||||
; R6: $v0 = ADDiu $zero, 1
|
||||
; R6: }
|
||||
; PIC-LABEL: name: a
|
||||
; PIC: bb.0.entry:
|
||||
; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
|
||||
; PIC: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
|
||||
; PIC: BC1NEZ $d0_64, %bb.3 {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1.entry:
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: BALC %bb.2, implicit-def $ra
|
||||
; PIC: bb.2.entry:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: JIC $at, 0, implicit-def $at
|
||||
; PIC: bb.3.if.then:
|
||||
; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
|
||||
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
|
||||
; PIC: $v0 = ADDiu $zero, 0
|
||||
; PIC: }
|
||||
; PIC: bb.4.return:
|
||||
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
|
||||
; PIC: $v0 = ADDiu $zero, 1
|
||||
; PIC: }
|
||||
bb.0.entry:
|
||||
successors: %bb.1(0x50000000), %bb.2(0x30000000)
|
||||
liveins: $d12_64, $d14_64
|
||||
|
||||
$f0 = CMP_EQ_D killed $d12_64, killed $d14_64
|
||||
BC1EQZ killed $d0_64, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.if.then:
|
||||
INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
|
||||
$v0 = ADDiu $zero, 0
|
||||
PseudoReturn undef $ra, implicit killed $v0
|
||||
|
||||
bb.2.return:
|
||||
$v0 = ADDiu $zero, 1
|
||||
PseudoReturn undef $ra, implicit killed $v0
|
||||
|
||||
...
|
||||
---
|
||||
name: b
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$d12_64', virtual-reg: '' }
|
||||
- { reg: '$d14_64', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; R6-LABEL: name: b
|
||||
; R6: bb.0.entry:
|
||||
; R6: successors: %bb.2(0x50000000), %bb.1(0x30000000)
|
||||
; R6: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
|
||||
; R6: BC1EQZ $d0_64, %bb.2 {
|
||||
; R6: NOP
|
||||
; R6: }
|
||||
; R6: bb.1.entry:
|
||||
; R6: successors: %bb.3(0x80000000)
|
||||
; R6: BC %bb.3
|
||||
; R6: bb.2.if.then:
|
||||
; R6: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
|
||||
; R6: PseudoReturn undef $ra, implicit killed $v0 {
|
||||
; R6: $v0 = ADDiu $zero, 0
|
||||
; R6: }
|
||||
; R6: bb.3.return:
|
||||
; R6: PseudoReturn undef $ra, implicit killed $v0 {
|
||||
; R6: $v0 = ADDiu $zero, 1
|
||||
; R6: }
|
||||
; PIC-LABEL: name: b
|
||||
; PIC: bb.0.entry:
|
||||
; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
|
||||
; PIC: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
|
||||
; PIC: BC1EQZ $d0_64, %bb.3 {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1.entry:
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: BALC %bb.2, implicit-def $ra
|
||||
; PIC: bb.2.entry:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: JIC $at, 0, implicit-def $at
|
||||
; PIC: bb.3.if.then:
|
||||
; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
|
||||
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
|
||||
; PIC: $v0 = ADDiu $zero, 0
|
||||
; PIC: }
|
||||
; PIC: bb.4.return:
|
||||
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
|
||||
; PIC: $v0 = ADDiu $zero, 1
|
||||
; PIC: }
|
||||
bb.0.entry:
|
||||
successors: %bb.1(0x50000000), %bb.2(0x30000000)
|
||||
liveins: $d12_64, $d14_64
|
||||
|
||||
$f0 = CMP_EQ_D killed $d12_64, killed $d14_64
|
||||
BC1NEZ killed $d0_64, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.if.then:
|
||||
INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
|
||||
$v0 = ADDiu $zero, 0
|
||||
PseudoReturn undef $ra, implicit killed $v0
|
||||
|
||||
bb.2.return:
|
||||
$v0 = ADDiu $zero, 1
|
||||
PseudoReturn undef $ra, implicit killed $v0
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,848 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=mips-mti-linux-gnu -mattr=+micromips -o - %s -start-before mips-delay-slot-filler -stop-after mips-long-branch | FileCheck %s --check-prefix=MM
|
||||
# RUN: llc -mtriple=mips-mti-linux-gnu -mattr=+micromips -o - %s -start-before mips-delay-slot-filler -stop-after mips-long-branch -relocation-model=pic | FileCheck %s --check-prefix=PIC
|
||||
|
||||
# Test the long branch expansion of various branches
|
||||
|
||||
--- |
|
||||
define void @expand_BEQ_MM(i1 %a) {
|
||||
br i1 %a, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
br label %tail
|
||||
|
||||
tail:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @expand_BGEZ_MM(i1 %a) {
|
||||
br i1 %a, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
br label %tail
|
||||
|
||||
tail:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @expand_BGTZ_MM(i1 %a) {
|
||||
br i1 %a, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
br label %tail
|
||||
|
||||
tail:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @expand_BLEZ_MM(i1 %a) {
|
||||
br i1 %a, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
br label %tail
|
||||
|
||||
tail:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @expand_BLTZ_MM(i1 %a) {
|
||||
br i1 %a, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
br label %tail
|
||||
|
||||
tail:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @expand_BNE_MM(i1 %a) {
|
||||
br i1 %a, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
br label %tail
|
||||
|
||||
tail:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @expand_BEQZ16_MM(i1 %a) {
|
||||
br i1 %a, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
br label %tail
|
||||
|
||||
tail:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @expand_BNEZ16_MM(i1 %a) {
|
||||
br i1 %a, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
br label %tail
|
||||
|
||||
tail:
|
||||
ret void
|
||||
}
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BEQ_MM
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MM-LABEL: name: expand_BEQ_MM
|
||||
; MM: bb.0 (%ir-block.0):
|
||||
; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MM: renamable $at = ANDi killed renamable $a0, 1
|
||||
; MM: BNEZC_MM $at, %bb.2, implicit-def $at
|
||||
; MM: bb.1 (%ir-block.0):
|
||||
; MM: successors: %bb.3(0x80000000)
|
||||
; MM: J %bb.3, implicit-def $at {
|
||||
; MM: NOP
|
||||
; MM: }
|
||||
; MM: bb.2.iftrue:
|
||||
; MM: successors: %bb.3(0x80000000)
|
||||
; MM: INLINEASM &".space 131068", 1
|
||||
; MM: bb.3.tail:
|
||||
; MM: JRC16_MM undef $ra
|
||||
; PIC-LABEL: name: expand_BEQ_MM
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: renamable $at = ANDi killed renamable $a0, 1
|
||||
; PIC: BNEZC_MM $at, %bb.3, implicit-def $at
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: JR $at {
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: JRC16_MM undef $ra
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0
|
||||
|
||||
renamable $at = ANDi killed renamable $a0, 1
|
||||
BEQ_MM killed renamable $at, $zero, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
successors: %bb.2(0x80000000)
|
||||
|
||||
INLINEASM &".space 131068", 1
|
||||
|
||||
bb.2.tail:
|
||||
PseudoReturn undef $ra
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BGEZ_MM
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MM-LABEL: name: expand_BGEZ_MM
|
||||
; MM: bb.0 (%ir-block.0):
|
||||
; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MM: renamable $at = ANDi killed renamable $a0, 1
|
||||
; MM: BLTZ_MM $at, %bb.2, implicit-def $at {
|
||||
; MM: NOP
|
||||
; MM: }
|
||||
; MM: bb.1 (%ir-block.0):
|
||||
; MM: successors: %bb.3(0x80000000)
|
||||
; MM: J %bb.3, implicit-def $at {
|
||||
; MM: NOP
|
||||
; MM: }
|
||||
; MM: bb.2.iftrue:
|
||||
; MM: successors: %bb.3(0x80000000)
|
||||
; MM: INLINEASM &".space 131068", 1
|
||||
; MM: bb.3.tail:
|
||||
; MM: JRC16_MM undef $ra
|
||||
; PIC-LABEL: name: expand_BGEZ_MM
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: renamable $at = ANDi killed renamable $a0, 1
|
||||
; PIC: BLTZ_MM $at, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: JR $at {
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: JRC16_MM undef $ra
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0
|
||||
|
||||
renamable $at = ANDi killed renamable $a0, 1
|
||||
BGEZ_MM killed renamable $at, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
successors: %bb.2(0x80000000)
|
||||
|
||||
INLINEASM &".space 131068", 1
|
||||
|
||||
bb.2.tail:
|
||||
PseudoReturn undef $ra
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BGTZ_MM
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MM-LABEL: name: expand_BGTZ_MM
|
||||
; MM: bb.0 (%ir-block.0):
|
||||
; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MM: renamable $at = ANDi killed renamable $a0, 1
|
||||
; MM: BLEZ_MM $at, %bb.2, implicit-def $at {
|
||||
; MM: NOP
|
||||
; MM: }
|
||||
; MM: bb.1 (%ir-block.0):
|
||||
; MM: successors: %bb.3(0x80000000)
|
||||
; MM: J %bb.3, implicit-def $at {
|
||||
; MM: NOP
|
||||
; MM: }
|
||||
; MM: bb.2.iftrue:
|
||||
; MM: successors: %bb.3(0x80000000)
|
||||
; MM: INLINEASM &".space 131068", 1
|
||||
; MM: bb.3.tail:
|
||||
; MM: JRC16_MM undef $ra
|
||||
; PIC-LABEL: name: expand_BGTZ_MM
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: renamable $at = ANDi killed renamable $a0, 1
|
||||
; PIC: BLEZ_MM $at, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: JR $at {
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: JRC16_MM undef $ra
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0
|
||||
|
||||
renamable $at = ANDi killed renamable $a0, 1
|
||||
BGTZ_MM killed renamable $at, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
successors: %bb.2(0x80000000)
|
||||
|
||||
INLINEASM &".space 131068", 1
|
||||
|
||||
bb.2.tail:
|
||||
PseudoReturn undef $ra
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BLEZ_MM
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MM-LABEL: name: expand_BLEZ_MM
|
||||
; MM: bb.0 (%ir-block.0):
|
||||
; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MM: renamable $at = ANDi killed renamable $a0, 1
|
||||
; MM: BGTZ_MM $at, %bb.2, implicit-def $at {
|
||||
; MM: NOP
|
||||
; MM: }
|
||||
; MM: bb.1 (%ir-block.0):
|
||||
; MM: successors: %bb.3(0x80000000)
|
||||
; MM: J %bb.3, implicit-def $at {
|
||||
; MM: NOP
|
||||
; MM: }
|
||||
; MM: bb.2.iftrue:
|
||||
; MM: successors: %bb.3(0x80000000)
|
||||
; MM: INLINEASM &".space 131068", 1
|
||||
; MM: bb.3.tail:
|
||||
; MM: JRC16_MM undef $ra
|
||||
; PIC-LABEL: name: expand_BLEZ_MM
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: renamable $at = ANDi killed renamable $a0, 1
|
||||
; PIC: BGTZ_MM $at, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: JR $at {
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: JRC16_MM undef $ra
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0
|
||||
|
||||
renamable $at = ANDi killed renamable $a0, 1
|
||||
BLEZ_MM killed renamable $at, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
successors: %bb.2(0x80000000)
|
||||
|
||||
INLINEASM &".space 131068", 1
|
||||
|
||||
bb.2.tail:
|
||||
PseudoReturn undef $ra
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BLTZ_MM
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MM-LABEL: name: expand_BLTZ_MM
|
||||
; MM: bb.0 (%ir-block.0):
|
||||
; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MM: renamable $at = ANDi killed renamable $a0, 1
|
||||
; MM: BGEZ_MM $at, %bb.2, implicit-def $at {
|
||||
; MM: NOP
|
||||
; MM: }
|
||||
; MM: bb.1 (%ir-block.0):
|
||||
; MM: successors: %bb.3(0x80000000)
|
||||
; MM: J %bb.3, implicit-def $at {
|
||||
; MM: NOP
|
||||
; MM: }
|
||||
; MM: bb.2.iftrue:
|
||||
; MM: successors: %bb.3(0x80000000)
|
||||
; MM: INLINEASM &".space 131068", 1
|
||||
; MM: bb.3.tail:
|
||||
; MM: JRC16_MM undef $ra
|
||||
; PIC-LABEL: name: expand_BLTZ_MM
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: renamable $at = ANDi killed renamable $a0, 1
|
||||
; PIC: BGEZ_MM $at, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: JR $at {
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: JRC16_MM undef $ra
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0
|
||||
|
||||
renamable $at = ANDi killed renamable $a0, 1
|
||||
BLTZ_MM killed renamable $at, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
successors: %bb.2(0x80000000)
|
||||
|
||||
INLINEASM &".space 131068", 1
|
||||
|
||||
bb.2.tail:
|
||||
PseudoReturn undef $ra
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BNE_MM
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MM-LABEL: name: expand_BNE_MM
|
||||
; MM: bb.0 (%ir-block.0):
|
||||
; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MM: renamable $at = ANDi killed renamable $a0, 1
|
||||
; MM: BEQZC_MM $at, %bb.2, implicit-def $at
|
||||
; MM: bb.1 (%ir-block.0):
|
||||
; MM: successors: %bb.3(0x80000000)
|
||||
; MM: J %bb.3, implicit-def $at {
|
||||
; MM: NOP
|
||||
; MM: }
|
||||
; MM: bb.2.iftrue:
|
||||
; MM: successors: %bb.3(0x80000000)
|
||||
; MM: INLINEASM &".space 131068", 1
|
||||
; MM: bb.3.tail:
|
||||
; MM: JRC16_MM undef $ra
|
||||
; PIC-LABEL: name: expand_BNE_MM
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: renamable $at = ANDi killed renamable $a0, 1
|
||||
; PIC: BEQZC_MM $at, %bb.3, implicit-def $at
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: JR $at {
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: JRC16_MM undef $ra
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0
|
||||
|
||||
renamable $at = ANDi killed renamable $a0, 1
|
||||
BNE_MM killed renamable $at, $zero, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
successors: %bb.2(0x80000000)
|
||||
|
||||
INLINEASM &".space 131068", 1
|
||||
|
||||
bb.2.tail:
|
||||
PseudoReturn undef $ra
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BEQZ16_MM
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MM-LABEL: name: expand_BEQZ16_MM
|
||||
; MM: bb.0 (%ir-block.0):
|
||||
; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MM: renamable $v0 = ANDi killed renamable $a0, 1
|
||||
; MM: BNEZ16_MM $v0, %bb.2, implicit-def $at {
|
||||
; MM: NOP
|
||||
; MM: }
|
||||
; MM: bb.1 (%ir-block.0):
|
||||
; MM: successors: %bb.3(0x80000000)
|
||||
; MM: J %bb.3, implicit-def $at {
|
||||
; MM: NOP
|
||||
; MM: }
|
||||
; MM: bb.2.iftrue:
|
||||
; MM: successors: %bb.3(0x80000000)
|
||||
; MM: INLINEASM &".space 131068", 1
|
||||
; MM: bb.3.tail:
|
||||
; MM: JRC16_MM undef $ra
|
||||
; PIC-LABEL: name: expand_BEQZ16_MM
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: renamable $v0 = ANDi killed renamable $a0, 1
|
||||
; PIC: BNEZ16_MM $v0, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: JR $at {
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: JRC16_MM undef $ra
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0
|
||||
|
||||
renamable $v0 = ANDi killed renamable $a0, 1
|
||||
BEQZ16_MM killed renamable $v0, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
successors: %bb.2(0x80000000)
|
||||
|
||||
INLINEASM &".space 131068", 1
|
||||
|
||||
bb.2.tail:
|
||||
PseudoReturn undef $ra
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BNEZ16_MM
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MM-LABEL: name: expand_BNEZ16_MM
|
||||
; MM: bb.0 (%ir-block.0):
|
||||
; MM: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MM: renamable $v0 = ANDi killed renamable $a0, 1
|
||||
; MM: BEQZ16_MM $v0, %bb.2, implicit-def $at {
|
||||
; MM: NOP
|
||||
; MM: }
|
||||
; MM: bb.1 (%ir-block.0):
|
||||
; MM: successors: %bb.3(0x80000000)
|
||||
; MM: J %bb.3, implicit-def $at {
|
||||
; MM: NOP
|
||||
; MM: }
|
||||
; MM: bb.2.iftrue:
|
||||
; MM: successors: %bb.3(0x80000000)
|
||||
; MM: INLINEASM &".space 131068", 1
|
||||
; MM: bb.3.tail:
|
||||
; MM: JRC16_MM undef $ra
|
||||
; PIC-LABEL: name: expand_BNEZ16_MM
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: renamable $v0 = ANDi killed renamable $a0, 1
|
||||
; PIC: BEQZ16_MM $v0, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: JR $at {
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: JRC16_MM undef $ra
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0
|
||||
|
||||
renamable $v0 = ANDi killed renamable $a0, 1
|
||||
BNEZ16_MM killed renamable $v0, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
successors: %bb.2(0x80000000)
|
||||
|
||||
INLINEASM &".space 131068", 1
|
||||
|
||||
bb.2.tail:
|
||||
PseudoReturn undef $ra
|
||||
|
||||
...
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,692 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=mips64-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch | FileCheck %s --check-prefix=MIPS64
|
||||
# RUN: llc -mtriple=mips64-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-long-branch -relocation-model=pic | FileCheck %s --check-prefix=PIC
|
||||
|
||||
# Test the long branch expansion of various branches
|
||||
|
||||
--- |
|
||||
define i64 @expand_BEQ64(i64 %a, i64 %b) {
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
br i1 %cmp, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
ret i64 1
|
||||
|
||||
tail:
|
||||
ret i64 0
|
||||
}
|
||||
|
||||
define i64 @expand_BNE64(i64 %a, i64 %b) {
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
br i1 %cmp, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
ret i64 1
|
||||
|
||||
tail:
|
||||
ret i64 0
|
||||
}
|
||||
|
||||
define i64 @expand_BGEZ64(i64 %a, i64 %b) {
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
br i1 %cmp, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
ret i64 1
|
||||
|
||||
tail:
|
||||
ret i64 0
|
||||
}
|
||||
|
||||
define i64 @expand_BGTZ64(i64 %a, i64 %b) {
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
br i1 %cmp, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
ret i64 1
|
||||
|
||||
tail:
|
||||
ret i64 0
|
||||
}
|
||||
|
||||
define i64 @expand_BLEZ64(i64 %a, i64 %b) {
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
br i1 %cmp, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
ret i64 1
|
||||
|
||||
tail:
|
||||
ret i64 0
|
||||
}
|
||||
|
||||
define i64 @expand_BLTZ64(i64 %a, i64 %b) {
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
br i1 %cmp, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
ret i64 1
|
||||
|
||||
tail:
|
||||
ret i64 0
|
||||
}
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BEQ64
|
||||
alignment: 3
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0_64', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MIPS64-LABEL: name: expand_BEQ64
|
||||
; MIPS64: bb.0 (%ir-block.0):
|
||||
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MIPS64: BNE64 $a0_64, $zero_64, %bb.2, implicit-def $at {
|
||||
; MIPS64: NOP
|
||||
; MIPS64: }
|
||||
; MIPS64: bb.1 (%ir-block.0):
|
||||
; MIPS64: successors: %bb.3(0x80000000)
|
||||
; MIPS64: J %bb.3, implicit-def $at {
|
||||
; MIPS64: NOP
|
||||
; MIPS64: }
|
||||
; MIPS64: bb.2.iftrue:
|
||||
; MIPS64: INLINEASM &".space 131068", 1
|
||||
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; MIPS64: $v0_64 = DADDiu $zero_64, 1
|
||||
; MIPS64: }
|
||||
; MIPS64: bb.3.tail:
|
||||
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; MIPS64: $v0_64 = DADDiu $zero_64, 0
|
||||
; MIPS64: }
|
||||
; PIC-LABEL: name: expand_BEQ64
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: BNE64 $a0_64, $zero_64, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp_64 = DADDiu $sp_64, -16
|
||||
; PIC: SD $ra_64, $sp_64, 0
|
||||
; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
|
||||
; PIC: $at_64 = DSLL $at_64, 16
|
||||
; PIC: BAL_BR %bb.2, implicit-def $ra {
|
||||
; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at_64 = DADDu $ra_64, $at_64
|
||||
; PIC: $ra_64 = LD $sp_64, 0
|
||||
; PIC: JR64 $at_64 {
|
||||
; PIC: $sp_64 = DADDiu $sp_64, 16
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; PIC: $v0_64 = DADDiu $zero_64, 1
|
||||
; PIC: }
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; PIC: $v0_64 = DADDiu $zero_64, 0
|
||||
; PIC: }
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0_64
|
||||
|
||||
BEQ64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
INLINEASM &".space 131068", 1
|
||||
$v0_64 = DADDiu $zero_64, 1
|
||||
PseudoReturn64 undef $ra_64, implicit killed $v0_64
|
||||
|
||||
bb.2.tail:
|
||||
$v0_64 = DADDiu $zero_64, 0
|
||||
PseudoReturn64 undef $ra_64, implicit killed $v0_64
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BNE64
|
||||
alignment: 3
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0_64', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MIPS64-LABEL: name: expand_BNE64
|
||||
; MIPS64: bb.0 (%ir-block.0):
|
||||
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MIPS64: BEQ64 $a0_64, $zero_64, %bb.2, implicit-def $at {
|
||||
; MIPS64: NOP
|
||||
; MIPS64: }
|
||||
; MIPS64: bb.1 (%ir-block.0):
|
||||
; MIPS64: successors: %bb.3(0x80000000)
|
||||
; MIPS64: J %bb.3, implicit-def $at {
|
||||
; MIPS64: NOP
|
||||
; MIPS64: }
|
||||
; MIPS64: bb.2.iftrue:
|
||||
; MIPS64: INLINEASM &".space 131068", 1
|
||||
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; MIPS64: $v0_64 = DADDiu $zero_64, 1
|
||||
; MIPS64: }
|
||||
; MIPS64: bb.3.tail:
|
||||
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; MIPS64: $v0_64 = DADDiu $zero_64, 0
|
||||
; MIPS64: }
|
||||
; PIC-LABEL: name: expand_BNE64
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: BEQ64 $a0_64, $zero_64, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp_64 = DADDiu $sp_64, -16
|
||||
; PIC: SD $ra_64, $sp_64, 0
|
||||
; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
|
||||
; PIC: $at_64 = DSLL $at_64, 16
|
||||
; PIC: BAL_BR %bb.2, implicit-def $ra {
|
||||
; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at_64 = DADDu $ra_64, $at_64
|
||||
; PIC: $ra_64 = LD $sp_64, 0
|
||||
; PIC: JR64 $at_64 {
|
||||
; PIC: $sp_64 = DADDiu $sp_64, 16
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; PIC: $v0_64 = DADDiu $zero_64, 1
|
||||
; PIC: }
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; PIC: $v0_64 = DADDiu $zero_64, 0
|
||||
; PIC: }
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0_64
|
||||
|
||||
BNE64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
INLINEASM &".space 131068", 1
|
||||
$v0_64 = DADDiu $zero_64, 1
|
||||
PseudoReturn64 undef $ra_64, implicit killed $v0_64
|
||||
|
||||
bb.2.tail:
|
||||
$v0_64 = DADDiu $zero_64, 0
|
||||
PseudoReturn64 undef $ra_64, implicit killed $v0_64
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BGEZ64
|
||||
alignment: 3
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0_64', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MIPS64-LABEL: name: expand_BGEZ64
|
||||
; MIPS64: bb.0 (%ir-block.0):
|
||||
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MIPS64: BLTZ64 $a0_64, %bb.2, implicit-def $at {
|
||||
; MIPS64: NOP
|
||||
; MIPS64: }
|
||||
; MIPS64: bb.1 (%ir-block.0):
|
||||
; MIPS64: successors: %bb.3(0x80000000)
|
||||
; MIPS64: J %bb.3, implicit-def $at {
|
||||
; MIPS64: NOP
|
||||
; MIPS64: }
|
||||
; MIPS64: bb.2.iftrue:
|
||||
; MIPS64: INLINEASM &".space 131068", 1
|
||||
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; MIPS64: $v0_64 = DADDiu $zero_64, 1
|
||||
; MIPS64: }
|
||||
; MIPS64: bb.3.tail:
|
||||
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; MIPS64: $v0_64 = DADDiu $zero_64, 0
|
||||
; MIPS64: }
|
||||
; PIC-LABEL: name: expand_BGEZ64
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: BLTZ64 $a0_64, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp_64 = DADDiu $sp_64, -16
|
||||
; PIC: SD $ra_64, $sp_64, 0
|
||||
; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
|
||||
; PIC: $at_64 = DSLL $at_64, 16
|
||||
; PIC: BAL_BR %bb.2, implicit-def $ra {
|
||||
; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at_64 = DADDu $ra_64, $at_64
|
||||
; PIC: $ra_64 = LD $sp_64, 0
|
||||
; PIC: JR64 $at_64 {
|
||||
; PIC: $sp_64 = DADDiu $sp_64, 16
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; PIC: $v0_64 = DADDiu $zero_64, 1
|
||||
; PIC: }
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; PIC: $v0_64 = DADDiu $zero_64, 0
|
||||
; PIC: }
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0_64
|
||||
|
||||
BGEZ64 killed renamable $a0_64, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
INLINEASM &".space 131068", 1
|
||||
$v0_64 = DADDiu $zero_64, 1
|
||||
PseudoReturn64 undef $ra_64, implicit killed $v0_64
|
||||
|
||||
bb.2.tail:
|
||||
$v0_64 = DADDiu $zero_64, 0
|
||||
PseudoReturn64 undef $ra_64, implicit killed $v0_64
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BGTZ64
|
||||
alignment: 3
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0_64', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MIPS64-LABEL: name: expand_BGTZ64
|
||||
; MIPS64: bb.0 (%ir-block.0):
|
||||
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MIPS64: BLEZ64 $a0_64, %bb.2, implicit-def $at {
|
||||
; MIPS64: NOP
|
||||
; MIPS64: }
|
||||
; MIPS64: bb.1 (%ir-block.0):
|
||||
; MIPS64: successors: %bb.3(0x80000000)
|
||||
; MIPS64: J %bb.3, implicit-def $at {
|
||||
; MIPS64: NOP
|
||||
; MIPS64: }
|
||||
; MIPS64: bb.2.iftrue:
|
||||
; MIPS64: INLINEASM &".space 131068", 1
|
||||
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; MIPS64: $v0_64 = DADDiu $zero_64, 1
|
||||
; MIPS64: }
|
||||
; MIPS64: bb.3.tail:
|
||||
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; MIPS64: $v0_64 = DADDiu $zero_64, 0
|
||||
; MIPS64: }
|
||||
; PIC-LABEL: name: expand_BGTZ64
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: BLEZ64 $a0_64, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp_64 = DADDiu $sp_64, -16
|
||||
; PIC: SD $ra_64, $sp_64, 0
|
||||
; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
|
||||
; PIC: $at_64 = DSLL $at_64, 16
|
||||
; PIC: BAL_BR %bb.2, implicit-def $ra {
|
||||
; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at_64 = DADDu $ra_64, $at_64
|
||||
; PIC: $ra_64 = LD $sp_64, 0
|
||||
; PIC: JR64 $at_64 {
|
||||
; PIC: $sp_64 = DADDiu $sp_64, 16
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; PIC: $v0_64 = DADDiu $zero_64, 1
|
||||
; PIC: }
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; PIC: $v0_64 = DADDiu $zero_64, 0
|
||||
; PIC: }
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0_64
|
||||
|
||||
BGTZ64 killed renamable $a0_64, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
INLINEASM &".space 131068", 1
|
||||
$v0_64 = DADDiu $zero_64, 1
|
||||
PseudoReturn64 undef $ra_64, implicit killed $v0_64
|
||||
|
||||
bb.2.tail:
|
||||
$v0_64 = DADDiu $zero_64, 0
|
||||
PseudoReturn64 undef $ra_64, implicit killed $v0_64
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BLEZ64
|
||||
alignment: 3
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0_64', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MIPS64-LABEL: name: expand_BLEZ64
|
||||
; MIPS64: bb.0 (%ir-block.0):
|
||||
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MIPS64: BGTZ64 $a0_64, %bb.2, implicit-def $at {
|
||||
; MIPS64: NOP
|
||||
; MIPS64: }
|
||||
; MIPS64: bb.1 (%ir-block.0):
|
||||
; MIPS64: successors: %bb.3(0x80000000)
|
||||
; MIPS64: J %bb.3, implicit-def $at {
|
||||
; MIPS64: NOP
|
||||
; MIPS64: }
|
||||
; MIPS64: bb.2.iftrue:
|
||||
; MIPS64: INLINEASM &".space 131068", 1
|
||||
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; MIPS64: $v0_64 = DADDiu $zero_64, 1
|
||||
; MIPS64: }
|
||||
; MIPS64: bb.3.tail:
|
||||
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; MIPS64: $v0_64 = DADDiu $zero_64, 0
|
||||
; MIPS64: }
|
||||
; PIC-LABEL: name: expand_BLEZ64
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: BGTZ64 $a0_64, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp_64 = DADDiu $sp_64, -16
|
||||
; PIC: SD $ra_64, $sp_64, 0
|
||||
; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
|
||||
; PIC: $at_64 = DSLL $at_64, 16
|
||||
; PIC: BAL_BR %bb.2, implicit-def $ra {
|
||||
; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at_64 = DADDu $ra_64, $at_64
|
||||
; PIC: $ra_64 = LD $sp_64, 0
|
||||
; PIC: JR64 $at_64 {
|
||||
; PIC: $sp_64 = DADDiu $sp_64, 16
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; PIC: $v0_64 = DADDiu $zero_64, 1
|
||||
; PIC: }
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; PIC: $v0_64 = DADDiu $zero_64, 0
|
||||
; PIC: }
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0_64
|
||||
|
||||
BLEZ64 killed renamable $a0_64, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
INLINEASM &".space 131068", 1
|
||||
$v0_64 = DADDiu $zero_64, 1
|
||||
PseudoReturn64 undef $ra_64, implicit killed $v0_64
|
||||
|
||||
bb.2.tail:
|
||||
$v0_64 = DADDiu $zero_64, 0
|
||||
PseudoReturn64 undef $ra_64, implicit killed $v0_64
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BLTZ64
|
||||
alignment: 3
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0_64', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MIPS64-LABEL: name: expand_BLTZ64
|
||||
; MIPS64: bb.0 (%ir-block.0):
|
||||
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MIPS64: BGEZ64 $a0_64, %bb.2, implicit-def $at {
|
||||
; MIPS64: NOP
|
||||
; MIPS64: }
|
||||
; MIPS64: bb.1 (%ir-block.0):
|
||||
; MIPS64: successors: %bb.3(0x80000000)
|
||||
; MIPS64: J %bb.3, implicit-def $at {
|
||||
; MIPS64: NOP
|
||||
; MIPS64: }
|
||||
; MIPS64: bb.2.iftrue:
|
||||
; MIPS64: INLINEASM &".space 131068", 1
|
||||
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; MIPS64: $v0_64 = DADDiu $zero_64, 1
|
||||
; MIPS64: }
|
||||
; MIPS64: bb.3.tail:
|
||||
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; MIPS64: $v0_64 = DADDiu $zero_64, 0
|
||||
; MIPS64: }
|
||||
; PIC-LABEL: name: expand_BLTZ64
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: BGEZ64 $a0_64, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp_64 = DADDiu $sp_64, -16
|
||||
; PIC: SD $ra_64, $sp_64, 0
|
||||
; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
|
||||
; PIC: $at_64 = DSLL $at_64, 16
|
||||
; PIC: BAL_BR %bb.2, implicit-def $ra {
|
||||
; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at_64 = DADDu $ra_64, $at_64
|
||||
; PIC: $ra_64 = LD $sp_64, 0
|
||||
; PIC: JR64 $at_64 {
|
||||
; PIC: $sp_64 = DADDiu $sp_64, 16
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; PIC: $v0_64 = DADDiu $zero_64, 1
|
||||
; PIC: }
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
||||
; PIC: $v0_64 = DADDiu $zero_64, 0
|
||||
; PIC: }
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0_64
|
||||
|
||||
BLTZ64 killed renamable $a0_64, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
INLINEASM &".space 131068", 1
|
||||
$v0_64 = DADDiu $zero_64, 1
|
||||
PseudoReturn64 undef $ra_64, implicit killed $v0_64
|
||||
|
||||
bb.2.tail:
|
||||
$v0_64 = DADDiu $zero_64, 0
|
||||
PseudoReturn64 undef $ra_64, implicit killed $v0_64
|
||||
|
||||
...
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,668 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=mips-mti-linux-gnu -o - %s -start-before mips-delay-slot-filler -stop-after mips-long-branch | FileCheck %s --check-prefix=MIPS
|
||||
# RUN: llc -mtriple=mips-mti-linux-gnu -o - %s -start-before mips-delay-slot-filler -stop-after mips-long-branch -relocation-model=pic | FileCheck %s --check-prefix=PIC
|
||||
|
||||
# Test the long branch expansion of various branches
|
||||
|
||||
--- |
|
||||
define void @expand_BEQ(i1 %a) {
|
||||
br i1 %a, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
br label %tail
|
||||
|
||||
tail:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @expand_BGEZ(i1 %a) {
|
||||
br i1 %a, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
br label %tail
|
||||
|
||||
tail:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @expand_BGTZ(i1 %a) {
|
||||
br i1 %a, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
br label %tail
|
||||
|
||||
tail:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @expand_BLEZ(i1 %a) {
|
||||
br i1 %a, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
br label %tail
|
||||
|
||||
tail:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @expand_BLTZ(i1 %a) {
|
||||
br i1 %a, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
br label %tail
|
||||
|
||||
tail:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @expand_BNE(i1 %a) {
|
||||
br i1 %a, label %iftrue, label %tail
|
||||
|
||||
iftrue:
|
||||
call void asm sideeffect ".space 131068", ""()
|
||||
br label %tail
|
||||
|
||||
tail:
|
||||
ret void
|
||||
}
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BEQ
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MIPS-LABEL: name: expand_BEQ
|
||||
; MIPS: bb.0 (%ir-block.0):
|
||||
; MIPS: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MIPS: renamable $at = ANDi killed renamable $a0, 1
|
||||
; MIPS: BNE $at, $zero, %bb.2, implicit-def $at {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; MIPS: bb.1 (%ir-block.0):
|
||||
; MIPS: successors: %bb.3(0x80000000)
|
||||
; MIPS: J %bb.3, implicit-def $at {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; MIPS: bb.2.iftrue:
|
||||
; MIPS: successors: %bb.3(0x80000000)
|
||||
; MIPS: INLINEASM &".space 131068", 1
|
||||
; MIPS: bb.3.tail:
|
||||
; MIPS: PseudoReturn undef $ra {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; PIC-LABEL: name: expand_BEQ
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: renamable $at = ANDi killed renamable $a0, 1
|
||||
; PIC: BNE $at, $zero, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: BAL_BR %bb.2, implicit-def $ra {
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: JR $at {
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: PseudoReturn undef $ra {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0
|
||||
|
||||
renamable $at = ANDi killed renamable $a0, 1
|
||||
BEQ killed renamable $at, $zero, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
successors: %bb.2(0x80000000)
|
||||
|
||||
INLINEASM &".space 131068", 1
|
||||
|
||||
bb.2.tail:
|
||||
PseudoReturn undef $ra
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BGEZ
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MIPS-LABEL: name: expand_BGEZ
|
||||
; MIPS: bb.0 (%ir-block.0):
|
||||
; MIPS: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MIPS: renamable $at = ANDi killed renamable $a0, 1
|
||||
; MIPS: BLTZ $at, %bb.2, implicit-def $at {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; MIPS: bb.1 (%ir-block.0):
|
||||
; MIPS: successors: %bb.3(0x80000000)
|
||||
; MIPS: J %bb.3, implicit-def $at {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; MIPS: bb.2.iftrue:
|
||||
; MIPS: successors: %bb.3(0x80000000)
|
||||
; MIPS: INLINEASM &".space 131068", 1
|
||||
; MIPS: bb.3.tail:
|
||||
; MIPS: PseudoReturn undef $ra {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; PIC-LABEL: name: expand_BGEZ
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: renamable $at = ANDi killed renamable $a0, 1
|
||||
; PIC: BLTZ $at, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: BAL_BR %bb.2, implicit-def $ra {
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: JR $at {
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: PseudoReturn undef $ra {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0
|
||||
|
||||
renamable $at = ANDi killed renamable $a0, 1
|
||||
BGEZ killed renamable $at, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
successors: %bb.2(0x80000000)
|
||||
|
||||
INLINEASM &".space 131068", 1
|
||||
|
||||
bb.2.tail:
|
||||
PseudoReturn undef $ra
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BGTZ
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MIPS-LABEL: name: expand_BGTZ
|
||||
; MIPS: bb.0 (%ir-block.0):
|
||||
; MIPS: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MIPS: renamable $at = ANDi killed renamable $a0, 1
|
||||
; MIPS: BLEZ $at, %bb.2, implicit-def $at {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; MIPS: bb.1 (%ir-block.0):
|
||||
; MIPS: successors: %bb.3(0x80000000)
|
||||
; MIPS: J %bb.3, implicit-def $at {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; MIPS: bb.2.iftrue:
|
||||
; MIPS: successors: %bb.3(0x80000000)
|
||||
; MIPS: INLINEASM &".space 131068", 1
|
||||
; MIPS: bb.3.tail:
|
||||
; MIPS: PseudoReturn undef $ra {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; PIC-LABEL: name: expand_BGTZ
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: renamable $at = ANDi killed renamable $a0, 1
|
||||
; PIC: BLEZ $at, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: BAL_BR %bb.2, implicit-def $ra {
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: JR $at {
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: PseudoReturn undef $ra {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0
|
||||
|
||||
renamable $at = ANDi killed renamable $a0, 1
|
||||
BGTZ killed renamable $at, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
successors: %bb.2(0x80000000)
|
||||
|
||||
INLINEASM &".space 131068", 1
|
||||
|
||||
bb.2.tail:
|
||||
PseudoReturn undef $ra
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BLEZ
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MIPS-LABEL: name: expand_BLEZ
|
||||
; MIPS: bb.0 (%ir-block.0):
|
||||
; MIPS: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MIPS: renamable $at = ANDi killed renamable $a0, 1
|
||||
; MIPS: BGTZ $at, %bb.2, implicit-def $at {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; MIPS: bb.1 (%ir-block.0):
|
||||
; MIPS: successors: %bb.3(0x80000000)
|
||||
; MIPS: J %bb.3, implicit-def $at {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; MIPS: bb.2.iftrue:
|
||||
; MIPS: successors: %bb.3(0x80000000)
|
||||
; MIPS: INLINEASM &".space 131068", 1
|
||||
; MIPS: bb.3.tail:
|
||||
; MIPS: PseudoReturn undef $ra {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; PIC-LABEL: name: expand_BLEZ
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: renamable $at = ANDi killed renamable $a0, 1
|
||||
; PIC: BGTZ $at, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: BAL_BR %bb.2, implicit-def $ra {
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: JR $at {
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: PseudoReturn undef $ra {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0
|
||||
|
||||
renamable $at = ANDi killed renamable $a0, 1
|
||||
BLEZ killed renamable $at, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
successors: %bb.2(0x80000000)
|
||||
|
||||
INLINEASM &".space 131068", 1
|
||||
|
||||
bb.2.tail:
|
||||
PseudoReturn undef $ra
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BLTZ
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MIPS-LABEL: name: expand_BLTZ
|
||||
; MIPS: bb.0 (%ir-block.0):
|
||||
; MIPS: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MIPS: renamable $at = ANDi killed renamable $a0, 1
|
||||
; MIPS: BGEZ $at, %bb.2, implicit-def $at {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; MIPS: bb.1 (%ir-block.0):
|
||||
; MIPS: successors: %bb.3(0x80000000)
|
||||
; MIPS: J %bb.3, implicit-def $at {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; MIPS: bb.2.iftrue:
|
||||
; MIPS: successors: %bb.3(0x80000000)
|
||||
; MIPS: INLINEASM &".space 131068", 1
|
||||
; MIPS: bb.3.tail:
|
||||
; MIPS: PseudoReturn undef $ra {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; PIC-LABEL: name: expand_BLTZ
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: renamable $at = ANDi killed renamable $a0, 1
|
||||
; PIC: BGEZ $at, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: BAL_BR %bb.2, implicit-def $ra {
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: JR $at {
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: PseudoReturn undef $ra {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0
|
||||
|
||||
renamable $at = ANDi killed renamable $a0, 1
|
||||
BLTZ killed renamable $at, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
successors: %bb.2(0x80000000)
|
||||
|
||||
INLINEASM &".space 131068", 1
|
||||
|
||||
bb.2.tail:
|
||||
PseudoReturn undef $ra
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: expand_BNE
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$a0', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 1
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
; MIPS-LABEL: name: expand_BNE
|
||||
; MIPS: bb.0 (%ir-block.0):
|
||||
; MIPS: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
; MIPS: renamable $at = ANDi killed renamable $a0, 1
|
||||
; MIPS: BEQ $at, $zero, %bb.2, implicit-def $at {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; MIPS: bb.1 (%ir-block.0):
|
||||
; MIPS: successors: %bb.3(0x80000000)
|
||||
; MIPS: J %bb.3, implicit-def $at {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; MIPS: bb.2.iftrue:
|
||||
; MIPS: successors: %bb.3(0x80000000)
|
||||
; MIPS: INLINEASM &".space 131068", 1
|
||||
; MIPS: bb.3.tail:
|
||||
; MIPS: PseudoReturn undef $ra {
|
||||
; MIPS: NOP
|
||||
; MIPS: }
|
||||
; PIC-LABEL: name: expand_BNE
|
||||
; PIC: bb.0 (%ir-block.0):
|
||||
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
||||
; PIC: renamable $at = ANDi killed renamable $a0, 1
|
||||
; PIC: BEQ $at, $zero, %bb.3, implicit-def $at {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
; PIC: bb.1 (%ir-block.0):
|
||||
; PIC: successors: %bb.2(0x80000000)
|
||||
; PIC: $sp = ADDiu $sp, -8
|
||||
; PIC: SW $ra, $sp, 0
|
||||
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
|
||||
; PIC: BAL_BR %bb.2, implicit-def $ra {
|
||||
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
|
||||
; PIC: }
|
||||
; PIC: bb.2 (%ir-block.0):
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: $at = ADDu $ra, $at
|
||||
; PIC: $ra = LW $sp, 0
|
||||
; PIC: JR $at {
|
||||
; PIC: $sp = ADDiu $sp, 8
|
||||
; PIC: }
|
||||
; PIC: bb.3.iftrue:
|
||||
; PIC: successors: %bb.4(0x80000000)
|
||||
; PIC: INLINEASM &".space 131068", 1
|
||||
; PIC: bb.4.tail:
|
||||
; PIC: PseudoReturn undef $ra {
|
||||
; PIC: NOP
|
||||
; PIC: }
|
||||
bb.0 (%ir-block.0):
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
liveins: $a0
|
||||
|
||||
renamable $at = ANDi killed renamable $a0, 1
|
||||
BNE killed renamable $at, $zero, %bb.2, implicit-def $at
|
||||
|
||||
bb.1.iftrue:
|
||||
successors: %bb.2(0x80000000)
|
||||
|
||||
INLINEASM &".space 131068", 1
|
||||
|
||||
bb.2.tail:
|
||||
PseudoReturn undef $ra
|
||||
|
||||
...
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue