[DAGCombiner] Extending pattern detection for vector shuffle.
If all the operands of a BUILD_VECTOR extract elements from same vector then split the vector efficiently based on the maximum vector access index. Committed on behalf of @jbhateja (Jatin Bhateja) Differential Revision: https://reviews.llvm.org/D35788 llvm-svn: 310058
This commit is contained in:
Simon Pilgrim
parent
5c7aaa5ff3
commit
5c63586489
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@ -14133,10 +14133,18 @@ SDValue DAGCombiner::createBuildVecShuffle(const SDLoc &DL, SDNode *N,
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EVT InVT1 = VecIn1.getValueType();
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EVT InVT2 = VecIn2.getNode() ? VecIn2.getValueType() : InVT1;
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unsigned Vec2Offset = InVT1.getVectorNumElements();
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unsigned Vec2Offset = 0;
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unsigned NumElems = VT.getVectorNumElements();
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unsigned ShuffleNumElems = NumElems;
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// In case both the input vectors are extracted from same base
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// vector we do not need extra added to the end (Vec2Offset) while
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// computing shuffle mask.
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if (!VecIn2 || !(VecIn1.getOpcode() == ISD::EXTRACT_SUBVECTOR) ||
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!(VecIn2.getOpcode() == ISD::EXTRACT_SUBVECTOR) ||
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!(VecIn1.getOperand(0) == VecIn2.getOperand(0)))
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Vec2Offset = InVT1.getVectorNumElements();
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// We can't generate a shuffle node with mismatched input and output types.
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// Try to make the types match the type of the output.
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if (InVT1 != VT || InVT2 != VT) {
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@ -14283,7 +14291,6 @@ SDValue DAGCombiner::reduceBuildVecToShuffle(SDNode *N) {
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if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
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!isa<ConstantSDNode>(Op.getOperand(1)))
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return SDValue();
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SDValue ExtractedFromVec = Op.getOperand(0);
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// All inputs must have the same element type as the output.
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@ -14306,6 +14313,44 @@ SDValue DAGCombiner::reduceBuildVecToShuffle(SDNode *N) {
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if (VecIn.size() < 2)
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return SDValue();
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// If all the Operands of BUILD_VECTOR extract from same
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// vector, then split the vector efficiently based on the maximum
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// vector access index and adjust the VectorMask and
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// VecIn accordingly.
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if (VecIn.size() == 2) {
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unsigned MaxIndex = 0;
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unsigned NearestPow2 = 0;
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SDValue Vec = VecIn.back();
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EVT InVT = Vec.getValueType();
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MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
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SmallVector<unsigned, 8> IndexVec(NumElems, 0);
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for (unsigned i = 0; i < NumElems; i++) {
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if (VectorMask[i] <= 0)
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continue;
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unsigned Index = N->getOperand(i).getConstantOperandVal(1);
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IndexVec[i] = Index;
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MaxIndex = std::max(MaxIndex, Index);
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}
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NearestPow2 = PowerOf2Ceil(MaxIndex);
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if ((NearestPow2 > 2) && ((NumElems * 2) < NearestPow2)) {
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unsigned SplitSize = NearestPow2 / 2;
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EVT SplitVT = EVT::getVectorVT(*DAG.getContext(),
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InVT.getVectorElementType(), SplitSize);
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SDValue VecIn2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, Vec,
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DAG.getConstant(SplitSize, DL, IdxTy));
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SDValue VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, Vec,
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DAG.getConstant(0, DL, IdxTy));
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VecIn.pop_back();
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VecIn.push_back(VecIn1);
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VecIn.push_back(VecIn2);
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for (unsigned i = 0; i < NumElems; i++)
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VectorMask[i] = (IndexVec[i] < SplitSize) ? 1 : 2;
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}
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}
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// TODO: We want to sort the vectors by descending length, so that adjacent
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// pairs have similar length, and the longer vector is always first in the
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// pair.
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@ -940,17 +940,17 @@ define void @interleave_24i16_out(<24 x i16>* %p, <8 x i16>* %q1, <8 x i16>* %q2
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;
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; AVX2-LABEL: interleave_24i16_out:
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; AVX2: # BB#0:
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; AVX2-NEXT: vmovdqu (%rdi), %ymm0
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; AVX2-NEXT: vmovdqu 32(%rdi), %xmm1
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; AVX2-NEXT: vpblendw {{.*#+}} ymm2 = ymm0[0,1],ymm1[2],ymm0[3,4],ymm1[5],ymm0[6,7,8,9],ymm1[10],ymm0[11,12],ymm1[13],ymm0[14,15]
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; AVX2-NEXT: vmovdqu 32(%rdi), %xmm0
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; AVX2-NEXT: vmovdqu (%rdi), %ymm1
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; AVX2-NEXT: vpblendw {{.*#+}} ymm2 = ymm1[0,1],ymm0[2],ymm1[3,4],ymm0[5],ymm1[6,7,8,9],ymm0[10],ymm1[11,12],ymm0[13],ymm1[14,15]
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; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm3
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; AVX2-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1],xmm2[2,3],xmm3[4],xmm2[5,6],xmm3[7]
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; AVX2-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[0,1,6,7,12,13,2,3,8,9,14,15,4,5,10,11]
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; AVX2-NEXT: vpblendw {{.*#+}} ymm3 = ymm1[0],ymm0[1,2],ymm1[3],ymm0[4,5],ymm1[6],ymm0[7],ymm1[8],ymm0[9,10],ymm1[11],ymm0[12,13],ymm1[14],ymm0[15]
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; AVX2-NEXT: vpblendw {{.*#+}} ymm3 = ymm0[0],ymm1[1,2],ymm0[3],ymm1[4,5],ymm0[6],ymm1[7],ymm0[8],ymm1[9,10],ymm0[11],ymm1[12,13],ymm0[14],ymm1[15]
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; AVX2-NEXT: vextracti128 $1, %ymm3, %xmm4
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; AVX2-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm4[2],xmm3[3,4],xmm4[5],xmm3[6,7]
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; AVX2-NEXT: vpshufb {{.*#+}} xmm3 = xmm3[2,3,8,9,14,15,4,5,10,11,0,1,6,7,12,13]
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; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3],ymm1[4],ymm0[5,6],ymm1[7],ymm0[8],ymm1[9],ymm0[10,11],ymm1[12],ymm0[13,14],ymm1[15]
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; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2,3],ymm0[4],ymm1[5,6],ymm0[7],ymm1[8],ymm0[9],ymm1[10,11],ymm0[12],ymm1[13,14],ymm0[15]
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; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3],xmm0[4,5],xmm1[6],xmm0[7]
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; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[4,5,10,11,0,1,6,7,12,13,2,3,8,9,14,15]
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@ -261,81 +261,33 @@ define <16 x i8> @trunc_shuffle_v64i8_01_05_09_13_17_21_25_29_33_37_41_45_49_53_
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;
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; AVX512BW-LABEL: trunc_shuffle_v64i8_01_05_09_13_17_21_25_29_33_37_41_45_49_53_57_62:
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; AVX512BW: # BB#0:
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; AVX512BW-NEXT: vpextrb $5, %xmm0, %eax
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; AVX512BW-NEXT: vpextrb $1, %xmm0, %ecx
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; AVX512BW-NEXT: vmovd %ecx, %xmm1
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; AVX512BW-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1
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; AVX512BW-NEXT: vpextrb $9, %xmm0, %eax
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; AVX512BW-NEXT: vpinsrb $2, %eax, %xmm1, %xmm1
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; AVX512BW-NEXT: vpextrb $13, %xmm0, %eax
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; AVX512BW-NEXT: vpinsrb $3, %eax, %xmm1, %xmm1
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; AVX512BW-NEXT: vextracti32x4 $1, %zmm0, %xmm2
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; AVX512BW-NEXT: vpextrb $1, %xmm2, %eax
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; AVX512BW-NEXT: vpinsrb $4, %eax, %xmm1, %xmm1
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; AVX512BW-NEXT: vpextrb $5, %xmm2, %eax
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; AVX512BW-NEXT: vpinsrb $5, %eax, %xmm1, %xmm1
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; AVX512BW-NEXT: vpextrb $9, %xmm2, %eax
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; AVX512BW-NEXT: vpinsrb $6, %eax, %xmm1, %xmm1
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; AVX512BW-NEXT: vpextrb $13, %xmm2, %eax
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; AVX512BW-NEXT: vpinsrb $7, %eax, %xmm1, %xmm1
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; AVX512BW-NEXT: vextracti32x4 $2, %zmm0, %xmm2
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; AVX512BW-NEXT: vpextrb $1, %xmm2, %eax
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; AVX512BW-NEXT: vpinsrb $8, %eax, %xmm1, %xmm1
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; AVX512BW-NEXT: vpextrb $5, %xmm2, %eax
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; AVX512BW-NEXT: vpinsrb $9, %eax, %xmm1, %xmm1
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; AVX512BW-NEXT: vpextrb $9, %xmm2, %eax
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; AVX512BW-NEXT: vpinsrb $10, %eax, %xmm1, %xmm1
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; AVX512BW-NEXT: vpextrb $13, %xmm2, %eax
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; AVX512BW-NEXT: vpinsrb $11, %eax, %xmm1, %xmm1
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; AVX512BW-NEXT: vextracti32x4 $3, %zmm0, %xmm0
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; AVX512BW-NEXT: vpextrb $1, %xmm0, %eax
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; AVX512BW-NEXT: vpinsrb $12, %eax, %xmm1, %xmm1
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; AVX512BW-NEXT: vpextrb $5, %xmm0, %eax
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; AVX512BW-NEXT: vpinsrb $13, %eax, %xmm1, %xmm1
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; AVX512BW-NEXT: vpextrb $9, %xmm0, %eax
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; AVX512BW-NEXT: vpinsrb $14, %eax, %xmm1, %xmm1
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; AVX512BW-NEXT: vpextrb $14, %xmm0, %eax
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; AVX512BW-NEXT: vpinsrb $15, %eax, %xmm1, %xmm0
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; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm2 = <1,5,9,13,u,u,u,u,u,u,u,u,u,u,u,u>
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; AVX512BW-NEXT: vpshufb %xmm2, %xmm1, %xmm1
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; AVX512BW-NEXT: vpshufb %xmm2, %xmm0, %xmm2
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; AVX512BW-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
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; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm0
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; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm2
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; AVX512BW-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[u,u,u,u,1,5,9,14,u,u,u,u,u,u,u,u]
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; AVX512BW-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[u,u,u,u,1,5,9,13,u,u,u,u,u,u,u,u]
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; AVX512BW-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
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; AVX512BW-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
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; AVX512BW-NEXT: vzeroupper
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; AVX512BW-NEXT: retq
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;
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; AVX512BWVL-LABEL: trunc_shuffle_v64i8_01_05_09_13_17_21_25_29_33_37_41_45_49_53_57_62:
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; AVX512BWVL: # BB#0:
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; AVX512BWVL-NEXT: vpextrb $5, %xmm0, %eax
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; AVX512BWVL-NEXT: vpextrb $1, %xmm0, %ecx
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; AVX512BWVL-NEXT: vmovd %ecx, %xmm1
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; AVX512BWVL-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1
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; AVX512BWVL-NEXT: vpextrb $9, %xmm0, %eax
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; AVX512BWVL-NEXT: vpinsrb $2, %eax, %xmm1, %xmm1
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; AVX512BWVL-NEXT: vpextrb $13, %xmm0, %eax
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; AVX512BWVL-NEXT: vpinsrb $3, %eax, %xmm1, %xmm1
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; AVX512BWVL-NEXT: vextracti32x4 $1, %zmm0, %xmm2
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; AVX512BWVL-NEXT: vpextrb $1, %xmm2, %eax
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; AVX512BWVL-NEXT: vpinsrb $4, %eax, %xmm1, %xmm1
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; AVX512BWVL-NEXT: vpextrb $5, %xmm2, %eax
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; AVX512BWVL-NEXT: vpinsrb $5, %eax, %xmm1, %xmm1
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; AVX512BWVL-NEXT: vpextrb $9, %xmm2, %eax
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; AVX512BWVL-NEXT: vpinsrb $6, %eax, %xmm1, %xmm1
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; AVX512BWVL-NEXT: vpextrb $13, %xmm2, %eax
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; AVX512BWVL-NEXT: vpinsrb $7, %eax, %xmm1, %xmm1
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; AVX512BWVL-NEXT: vextracti32x4 $2, %zmm0, %xmm2
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; AVX512BWVL-NEXT: vpextrb $1, %xmm2, %eax
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; AVX512BWVL-NEXT: vpinsrb $8, %eax, %xmm1, %xmm1
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; AVX512BWVL-NEXT: vpextrb $5, %xmm2, %eax
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; AVX512BWVL-NEXT: vpinsrb $9, %eax, %xmm1, %xmm1
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; AVX512BWVL-NEXT: vpextrb $9, %xmm2, %eax
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; AVX512BWVL-NEXT: vpinsrb $10, %eax, %xmm1, %xmm1
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; AVX512BWVL-NEXT: vpextrb $13, %xmm2, %eax
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; AVX512BWVL-NEXT: vpinsrb $11, %eax, %xmm1, %xmm1
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; AVX512BWVL-NEXT: vextracti32x4 $3, %zmm0, %xmm0
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; AVX512BWVL-NEXT: vpextrb $1, %xmm0, %eax
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; AVX512BWVL-NEXT: vpinsrb $12, %eax, %xmm1, %xmm1
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; AVX512BWVL-NEXT: vpextrb $5, %xmm0, %eax
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; AVX512BWVL-NEXT: vpinsrb $13, %eax, %xmm1, %xmm1
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; AVX512BWVL-NEXT: vpextrb $9, %xmm0, %eax
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; AVX512BWVL-NEXT: vpinsrb $14, %eax, %xmm1, %xmm1
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; AVX512BWVL-NEXT: vpextrb $14, %xmm0, %eax
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; AVX512BWVL-NEXT: vpinsrb $15, %eax, %xmm1, %xmm0
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; AVX512BWVL-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX512BWVL-NEXT: vmovdqa {{.*#+}} xmm2 = <1,5,9,13,u,u,u,u,u,u,u,u,u,u,u,u>
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; AVX512BWVL-NEXT: vpshufb %xmm2, %xmm1, %xmm1
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; AVX512BWVL-NEXT: vpshufb %xmm2, %xmm0, %xmm2
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; AVX512BWVL-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
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; AVX512BWVL-NEXT: vextracti64x4 $1, %zmm0, %ymm0
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; AVX512BWVL-NEXT: vextracti128 $1, %ymm0, %xmm2
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; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[u,u,u,u,1,5,9,14,u,u,u,u,u,u,u,u]
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; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[u,u,u,u,1,5,9,13,u,u,u,u,u,u,u,u]
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; AVX512BWVL-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
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; AVX512BWVL-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
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; AVX512BWVL-NEXT: vzeroupper
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; AVX512BWVL-NEXT: retq
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%res = shufflevector <64 x i8> %x, <64 x i8> %x, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 62>
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@ -295,13 +295,10 @@ define <8 x i32> @test_v16i32_1_3_5_7_9_11_13_15(<16 x i32> %v) {
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define <4 x i32> @test_v16i32_0_1_2_12 (<16 x i32> %v) {
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; ALL-LABEL: test_v16i32_0_1_2_12:
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; ALL: # BB#0:
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; ALL-NEXT: vpextrd $1, %xmm0, %eax
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; ALL-NEXT: vpinsrd $1, %eax, %xmm0, %xmm1
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; ALL-NEXT: vpextrd $2, %xmm0, %eax
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; ALL-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1
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; ALL-NEXT: vextracti32x4 $3, %zmm0, %xmm0
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; ALL-NEXT: vmovd %xmm0, %eax
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; ALL-NEXT: vpinsrd $3, %eax, %xmm1, %xmm0
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; ALL-NEXT: vextracti32x8 $1, %zmm0, %ymm1
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; ALL-NEXT: vextracti128 $1, %ymm1, %xmm1
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; ALL-NEXT: vpbroadcastd %xmm1, %xmm1
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; ALL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
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; ALL-NEXT: vzeroupper
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; ALL-NEXT: retq
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%res = shufflevector <16 x i32> %v, <16 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 12>
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@ -2726,20 +2726,17 @@ define <4 x i64> @test_v8i64_1257 (<8 x i64> %v) {
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define <2 x i64> @test_v8i64_2_5 (<8 x i64> %v) {
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; AVX512F-LABEL: test_v8i64_2_5:
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; AVX512F: # BB#0:
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; AVX512F-NEXT: vextracti32x4 $2, %zmm0, %xmm1
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; AVX512F-NEXT: vextracti32x4 $1, %zmm0, %xmm0
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; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm1
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; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0
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; AVX512F-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX512F-NEXT: vzeroupper
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; AVX512F-NEXT: retq
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;
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; AVX512F-32-LABEL: test_v8i64_2_5:
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; AVX512F-32: # BB#0:
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; AVX512F-32-NEXT: vextracti32x4 $1, %zmm0, %xmm1
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; AVX512F-32-NEXT: vextracti32x4 $2, %zmm0, %xmm0
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; AVX512F-32-NEXT: vpextrd $2, %xmm0, %eax
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; AVX512F-32-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1
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; AVX512F-32-NEXT: vpextrd $3, %xmm0, %eax
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; AVX512F-32-NEXT: vpinsrd $3, %eax, %xmm1, %xmm0
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; AVX512F-32-NEXT: vextracti64x4 $1, %zmm0, %ymm1
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; AVX512F-32-NEXT: vextracti128 $1, %ymm0, %xmm0
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; AVX512F-32-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX512F-32-NEXT: vzeroupper
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; AVX512F-32-NEXT: retl
|
||||
%res = shufflevector <8 x i64> %v, <8 x i64> undef, <2 x i32> <i32 2, i32 5>
|
||||
|
|
|
|||
|
|
@ -591,37 +591,37 @@ define <16 x i1> @interleaved_load_vf16_i8_stride4(<64 x i8>* %ptr) {
|
|||
; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
|
||||
; AVX2-NEXT: vpshufb %xmm4, %xmm2, %xmm2
|
||||
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm3
|
||||
; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = <u,u,u,u,1,5,9,13,u,u,u,u,u,u,u,u>
|
||||
; AVX2-NEXT: vpshufb %xmm4, %xmm3, %xmm5
|
||||
; AVX2-NEXT: vpshufb %xmm4, %xmm1, %xmm4
|
||||
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm5
|
||||
; AVX2-NEXT: vmovdqa {{.*#+}} xmm6 = <1,5,9,13,u,u,u,u,u,u,u,u,u,u,u,u>
|
||||
; AVX2-NEXT: vpshufb %xmm6, %xmm5, %xmm7
|
||||
; AVX2-NEXT: vpshufb %xmm6, %xmm0, %xmm6
|
||||
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm4 = xmm6[0,1],xmm4[2,3]
|
||||
; AVX2-NEXT: vpcmpeqb %xmm4, %xmm2, %xmm2
|
||||
; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = <u,u,u,u,2,6,10,14,u,u,u,u,u,u,u,u>
|
||||
; AVX2-NEXT: vpshufb %xmm4, %xmm3, %xmm6
|
||||
; AVX2-NEXT: vpshufb %xmm4, %xmm1, %xmm4
|
||||
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm4[0],xmm6[0],xmm4[1],xmm6[1]
|
||||
; AVX2-NEXT: vmovdqa {{.*#+}} xmm6 = <2,6,10,14,u,u,u,u,u,u,u,u,u,u,u,u>
|
||||
; AVX2-NEXT: vpshufb %xmm6, %xmm5, %xmm7
|
||||
; AVX2-NEXT: vpshufb %xmm6, %xmm0, %xmm6
|
||||
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm4 = xmm6[0,1],xmm4[2,3]
|
||||
; AVX2-NEXT: vmovdqa {{.*#+}} xmm6 = <u,u,u,u,3,7,11,15,u,u,u,u,u,u,u,u>
|
||||
; AVX2-NEXT: vpshufb %xmm6, %xmm3, %xmm3
|
||||
; AVX2-NEXT: vpshufb %xmm6, %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
|
||||
; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <3,7,11,15,u,u,u,u,u,u,u,u,u,u,u,u>
|
||||
; AVX2-NEXT: vpshufb %xmm3, %xmm5, %xmm5
|
||||
; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0
|
||||
; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <u,u,u,u,1,5,9,13,u,u,u,u,u,u,u,u>
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm4
|
||||
; AVX2-NEXT: vpshufb %xmm3, %xmm4, %xmm5
|
||||
; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm3
|
||||
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[1],xmm5[1]
|
||||
; AVX2-NEXT: vmovdqa {{.*#+}} xmm5 = <1,5,9,13,u,u,u,u,u,u,u,u,u,u,u,u>
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm6
|
||||
; AVX2-NEXT: vpshufb %xmm5, %xmm6, %xmm7
|
||||
; AVX2-NEXT: vpshufb %xmm5, %xmm0, %xmm5
|
||||
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm5 = xmm5[0],xmm7[0],xmm5[1],xmm7[1]
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm3 = xmm5[0,1],xmm3[2,3]
|
||||
; AVX2-NEXT: vpcmpeqb %xmm3, %xmm2, %xmm2
|
||||
; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <u,u,u,u,2,6,10,14,u,u,u,u,u,u,u,u>
|
||||
; AVX2-NEXT: vpshufb %xmm3, %xmm4, %xmm5
|
||||
; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm3
|
||||
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[1],xmm5[1]
|
||||
; AVX2-NEXT: vmovdqa {{.*#+}} xmm5 = <2,6,10,14,u,u,u,u,u,u,u,u,u,u,u,u>
|
||||
; AVX2-NEXT: vpshufb %xmm5, %xmm6, %xmm7
|
||||
; AVX2-NEXT: vpshufb %xmm5, %xmm0, %xmm5
|
||||
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm5 = xmm5[0],xmm7[0],xmm5[1],xmm7[1]
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm3 = xmm5[0,1],xmm3[2,3]
|
||||
; AVX2-NEXT: vmovdqa {{.*#+}} xmm5 = <u,u,u,u,3,7,11,15,u,u,u,u,u,u,u,u>
|
||||
; AVX2-NEXT: vpshufb %xmm5, %xmm4, %xmm4
|
||||
; AVX2-NEXT: vpshufb %xmm5, %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1]
|
||||
; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = <3,7,11,15,u,u,u,u,u,u,u,u,u,u,u,u>
|
||||
; AVX2-NEXT: vpshufb %xmm4, %xmm6, %xmm5
|
||||
; AVX2-NEXT: vpshufb %xmm4, %xmm0, %xmm0
|
||||
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
|
||||
; AVX2-NEXT: vpcmpeqb %xmm0, %xmm4, %xmm0
|
||||
; AVX2-NEXT: vpcmpeqb %xmm0, %xmm3, %xmm0
|
||||
; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
|
||||
; AVX2-NEXT: vpand %xmm1, %xmm2, %xmm2
|
||||
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
|
||||
|
|
@ -860,15 +860,15 @@ define <32 x i1> @interleaved_load_vf32_i8_stride4(<128 x i8>* %ptr) {
|
|||
; AVX512-NEXT: vpmovdw %zmm1, %ymm3
|
||||
; AVX512-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2
|
||||
; AVX512-NEXT: vpmovwb %zmm2, %ymm8
|
||||
; AVX512-NEXT: vmovdqa {{.*#+}} xmm7 = <u,u,u,u,1,5,9,13,u,u,u,u,u,u,u,u>
|
||||
; AVX512-NEXT: vextracti64x4 $1, %zmm1, %ymm14
|
||||
; AVX512-NEXT: vextracti128 $1, %ymm14, %xmm9
|
||||
; AVX512-NEXT: vmovdqa {{.*#+}} xmm7 = <u,u,u,u,1,5,9,13,u,u,u,u,u,u,u,u>
|
||||
; AVX512-NEXT: vpshufb %xmm7, %xmm9, %xmm4
|
||||
; AVX512-NEXT: vpshufb %xmm7, %xmm14, %xmm5
|
||||
; AVX512-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm5[0],xmm4[0],xmm5[1],xmm4[1]
|
||||
; AVX512-NEXT: vinserti128 $1, %xmm4, %ymm0, %ymm5
|
||||
; AVX512-NEXT: vmovdqa {{.*#+}} xmm3 = <1,5,9,13,u,u,u,u,u,u,u,u,u,u,u,u>
|
||||
; AVX512-NEXT: vextracti128 $1, %ymm1, %xmm10
|
||||
; AVX512-NEXT: vmovdqa {{.*#+}} xmm3 = <1,5,9,13,u,u,u,u,u,u,u,u,u,u,u,u>
|
||||
; AVX512-NEXT: vpshufb %xmm3, %xmm10, %xmm6
|
||||
; AVX512-NEXT: vpshufb %xmm3, %xmm1, %xmm4
|
||||
; AVX512-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm4[0],xmm6[0],xmm4[1],xmm6[1]
|
||||
|
|
|
|||
Loading…
Reference in New Issue