refactor the LowerOperation code out to individual functions for
each lowering, which is 'best practice'. llvm-svn: 48441
This commit is contained in:
Chris Lattner
parent
92dcf1e0c2
commit
5c5597a572
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@ -106,6 +106,8 @@ namespace {
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SparcTargetLowering(TargetMachine &TM);
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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int getVarArgsFrameOffset() const { return VarArgsFrameOffset; }
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/// computeMaskedBitsForTargetNode - Determine which of the bits specified
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/// in Mask are known to be either zero or one and return them in the
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/// KnownZero/KnownOne bitsets.
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@ -719,190 +721,212 @@ static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
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}
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}
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static SDOperand LowerGLOBALADDRESS(SDOperand Op, SelectionDAG &DAG) {
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GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
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SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
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SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
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SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
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return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
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}
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static SDOperand LowerCONSTANTPOOL(SDOperand Op, SelectionDAG &DAG) {
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ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
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Constant *C = N->getConstVal();
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SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
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SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
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SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
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return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
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}
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static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
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// Convert the fp value to integer in an FP register.
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assert(Op.getValueType() == MVT::i32);
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Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
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return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
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}
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static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
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assert(Op.getOperand(0).getValueType() == MVT::i32);
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SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
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// Convert the int value to FP in an FP register.
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return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
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}
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static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Chain = Op.getOperand(0);
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
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SDOperand LHS = Op.getOperand(2);
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SDOperand RHS = Op.getOperand(3);
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SDOperand Dest = Op.getOperand(4);
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unsigned Opc, SPCC = ~0U;
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// If this is a br_cc of a "setcc", and if the setcc got lowered into
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// an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
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LookThroughSetCC(LHS, RHS, CC, SPCC);
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// Get the condition flag.
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SDOperand CompareFlag;
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if (LHS.getValueType() == MVT::i32) {
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std::vector<MVT::ValueType> VTs;
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VTs.push_back(MVT::i32);
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VTs.push_back(MVT::Flag);
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SDOperand Ops[2] = { LHS, RHS };
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CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
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if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
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Opc = SPISD::BRICC;
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} else {
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CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
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if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
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Opc = SPISD::BRFCC;
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}
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return DAG.getNode(Opc, MVT::Other, Chain, Dest,
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DAG.getConstant(SPCC, MVT::i32), CompareFlag);
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}
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static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
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SDOperand LHS = Op.getOperand(0);
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SDOperand RHS = Op.getOperand(1);
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
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SDOperand TrueVal = Op.getOperand(2);
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SDOperand FalseVal = Op.getOperand(3);
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unsigned Opc, SPCC = ~0U;
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// If this is a select_cc of a "setcc", and if the setcc got lowered into
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// an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
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LookThroughSetCC(LHS, RHS, CC, SPCC);
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SDOperand CompareFlag;
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if (LHS.getValueType() == MVT::i32) {
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std::vector<MVT::ValueType> VTs;
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VTs.push_back(LHS.getValueType()); // subcc returns a value
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VTs.push_back(MVT::Flag);
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SDOperand Ops[2] = { LHS, RHS };
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CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
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Opc = SPISD::SELECT_ICC;
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if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
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} else {
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CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
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Opc = SPISD::SELECT_FCC;
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if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
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}
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return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
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DAG.getConstant(SPCC, MVT::i32), CompareFlag);
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}
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static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
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SparcTargetLowering &TLI) {
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// vastart just stores the address of the VarArgsFrameIndex slot into the
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// memory location argument.
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SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
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DAG.getRegister(SP::I6, MVT::i32),
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DAG.getConstant(TLI.getVarArgsFrameOffset(),
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MVT::i32));
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const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
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return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0);
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}
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static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG) {
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SDNode *Node = Op.Val;
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MVT::ValueType VT = Node->getValueType(0);
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SDOperand InChain = Node->getOperand(0);
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SDOperand VAListPtr = Node->getOperand(1);
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const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
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SDOperand VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0);
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// Increment the pointer, VAList, to the next vaarg
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SDOperand NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList,
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DAG.getConstant(MVT::getSizeInBits(VT)/8,
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MVT::i32));
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// Store the incremented VAList to the legalized pointer
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InChain = DAG.getStore(VAList.getValue(1), NextPtr,
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VAListPtr, SV, 0);
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// Load the actual argument out of the pointer VAList, unless this is an
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// f64 load.
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if (VT != MVT::f64)
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return DAG.getLoad(VT, InChain, VAList, NULL, 0);
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// Otherwise, load it as i64, then do a bitconvert.
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SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
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// Bit-Convert the value to f64.
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SDOperand Ops[2] = {
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DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
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V.getValue(1)
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};
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return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::f64, MVT::Other),
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Ops, 2);
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}
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static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Chain = Op.getOperand(0); // Legalize the chain.
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SDOperand Size = Op.getOperand(1); // Legalize the size.
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unsigned SPReg = SP::O6;
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SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
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SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value
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Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain
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// The resultant pointer is actually 16 words from the bottom of the stack,
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// to provide a register spill area.
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SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
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DAG.getConstant(96, MVT::i32));
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std::vector<MVT::ValueType> Tys;
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Tys.push_back(MVT::i32);
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Tys.push_back(MVT::Other);
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SDOperand Ops[2] = { NewVal, Chain };
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return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
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}
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static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Copy;
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switch(Op.getNumOperands()) {
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default:
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assert(0 && "Do not know how to return this many arguments!");
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abort();
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case 1:
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return SDOperand(); // ret void is legal
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case 3: {
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unsigned ArgReg;
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switch(Op.getOperand(1).getValueType()) {
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default: assert(0 && "Unknown type to return!");
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case MVT::i32: ArgReg = SP::I0; break;
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case MVT::f32: ArgReg = SP::F0; break;
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case MVT::f64: ArgReg = SP::D0; break;
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}
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Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
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SDOperand());
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break;
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}
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case 5:
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Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3),
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SDOperand());
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Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
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break;
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}
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return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
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}
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SDOperand SparcTargetLowering::
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LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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default: assert(0 && "Should not custom lower this!");
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// Frame & Return address. Currently unimplemented
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case ISD::RETURNADDR: return SDOperand();
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case ISD::FRAMEADDR: return SDOperand();
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case ISD::GlobalTLSAddress:
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assert(0 && "TLS not implemented for Sparc.");
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case ISD::GlobalAddress: {
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GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
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SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
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SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
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SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
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return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
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case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
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case ISD::ConstantPool: return LowerCONSTANTPOOL(Op, DAG);
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case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
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case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
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case ISD::BR_CC: return LowerBR_CC(Op, DAG);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
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case ISD::VAARG: return LowerVAARG(Op, DAG);
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case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
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case ISD::RET: return LowerRET(Op, DAG);
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}
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case ISD::ConstantPool: {
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Constant *C = cast<ConstantPoolSDNode>(Op)->getConstVal();
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SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32,
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cast<ConstantPoolSDNode>(Op)->getAlignment());
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SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
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SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
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return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
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}
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case ISD::FP_TO_SINT:
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// Convert the fp value to integer in an FP register.
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assert(Op.getValueType() == MVT::i32);
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Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
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return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
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case ISD::SINT_TO_FP: {
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assert(Op.getOperand(0).getValueType() == MVT::i32);
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SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
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// Convert the int value to FP in an FP register.
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return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
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}
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case ISD::BR_CC: {
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SDOperand Chain = Op.getOperand(0);
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
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SDOperand LHS = Op.getOperand(2);
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SDOperand RHS = Op.getOperand(3);
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SDOperand Dest = Op.getOperand(4);
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unsigned Opc, SPCC = ~0U;
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// If this is a br_cc of a "setcc", and if the setcc got lowered into
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// an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
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LookThroughSetCC(LHS, RHS, CC, SPCC);
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// Get the condition flag.
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SDOperand CompareFlag;
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if (LHS.getValueType() == MVT::i32) {
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std::vector<MVT::ValueType> VTs;
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VTs.push_back(MVT::i32);
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VTs.push_back(MVT::Flag);
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SDOperand Ops[2] = { LHS, RHS };
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CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
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if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
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Opc = SPISD::BRICC;
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} else {
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CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
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if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
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Opc = SPISD::BRFCC;
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}
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return DAG.getNode(Opc, MVT::Other, Chain, Dest,
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DAG.getConstant(SPCC, MVT::i32), CompareFlag);
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}
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case ISD::SELECT_CC: {
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SDOperand LHS = Op.getOperand(0);
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SDOperand RHS = Op.getOperand(1);
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
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SDOperand TrueVal = Op.getOperand(2);
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SDOperand FalseVal = Op.getOperand(3);
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unsigned Opc, SPCC = ~0U;
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// If this is a select_cc of a "setcc", and if the setcc got lowered into
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// an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
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LookThroughSetCC(LHS, RHS, CC, SPCC);
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SDOperand CompareFlag;
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if (LHS.getValueType() == MVT::i32) {
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std::vector<MVT::ValueType> VTs;
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VTs.push_back(LHS.getValueType()); // subcc returns a value
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VTs.push_back(MVT::Flag);
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SDOperand Ops[2] = { LHS, RHS };
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CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
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Opc = SPISD::SELECT_ICC;
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if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
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} else {
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CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
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Opc = SPISD::SELECT_FCC;
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if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
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}
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return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
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DAG.getConstant(SPCC, MVT::i32), CompareFlag);
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}
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case ISD::VASTART: {
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// vastart just stores the address of the VarArgsFrameIndex slot into the
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// memory location argument.
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SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
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DAG.getRegister(SP::I6, MVT::i32),
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DAG.getConstant(VarArgsFrameOffset, MVT::i32));
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const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
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return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0);
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}
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case ISD::VAARG: {
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SDNode *Node = Op.Val;
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MVT::ValueType VT = Node->getValueType(0);
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SDOperand InChain = Node->getOperand(0);
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SDOperand VAListPtr = Node->getOperand(1);
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const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
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SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, SV, 0);
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// Increment the pointer, VAList, to the next vaarg
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SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList,
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DAG.getConstant(MVT::getSizeInBits(VT)/8,
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getPointerTy()));
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// Store the incremented VAList to the legalized pointer
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InChain = DAG.getStore(VAList.getValue(1), NextPtr,
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VAListPtr, SV, 0);
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// Load the actual argument out of the pointer VAList, unless this is an
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// f64 load.
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if (VT != MVT::f64) {
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return DAG.getLoad(VT, InChain, VAList, NULL, 0);
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} else {
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// Otherwise, load it as i64, then do a bitconvert.
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SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
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std::vector<MVT::ValueType> Tys;
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Tys.push_back(MVT::f64);
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Tys.push_back(MVT::Other);
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// Bit-Convert the value to f64.
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SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
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V.getValue(1) };
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return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
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}
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}
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case ISD::DYNAMIC_STACKALLOC: {
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SDOperand Chain = Op.getOperand(0); // Legalize the chain.
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SDOperand Size = Op.getOperand(1); // Legalize the size.
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unsigned SPReg = SP::O6;
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SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
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SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value
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Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain
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// The resultant pointer is actually 16 words from the bottom of the stack,
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// to provide a register spill area.
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SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
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DAG.getConstant(96, MVT::i32));
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std::vector<MVT::ValueType> Tys;
|
||||
Tys.push_back(MVT::i32);
|
||||
Tys.push_back(MVT::Other);
|
||||
SDOperand Ops[2] = { NewVal, Chain };
|
||||
return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
|
||||
}
|
||||
case ISD::RET: {
|
||||
SDOperand Copy;
|
||||
|
||||
switch(Op.getNumOperands()) {
|
||||
default:
|
||||
assert(0 && "Do not know how to return this many arguments!");
|
||||
abort();
|
||||
case 1:
|
||||
return SDOperand(); // ret void is legal
|
||||
case 3: {
|
||||
unsigned ArgReg;
|
||||
switch(Op.getOperand(1).getValueType()) {
|
||||
default: assert(0 && "Unknown type to return!");
|
||||
case MVT::i32: ArgReg = SP::I0; break;
|
||||
case MVT::f32: ArgReg = SP::F0; break;
|
||||
case MVT::f64: ArgReg = SP::D0; break;
|
||||
}
|
||||
Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
|
||||
SDOperand());
|
||||
break;
|
||||
}
|
||||
case 5:
|
||||
Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3),
|
||||
SDOperand());
|
||||
Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
|
||||
break;
|
||||
}
|
||||
return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
|
||||
}
|
||||
// Frame & Return address. Currently unimplemented
|
||||
case ISD::RETURNADDR: break;
|
||||
case ISD::FRAMEADDR: break;
|
||||
}
|
||||
return SDOperand();
|
||||
}
|
||||
|
||||
MachineBasicBlock *
|
||||
|
|
|
|||
Loading…
Reference in New Issue