TwoAddressInstructionPass enhancement. After it converts a two address instruction into a 3-address one, sink it past the instruction that kills the read-mod-write register if its definition is used past the kill. This reduces the number of live register by one.
llvm-svn: 48333
This commit is contained in:
Evan Cheng
parent
fdc0748940
commit
5c26bde55e
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@ -37,8 +37,9 @@
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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@ -46,10 +47,22 @@ using namespace llvm;
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STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
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STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
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STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
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STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
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namespace {
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static cl::opt<int>
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SinkLimit("two-addr-sink-limit", cl::init(-1), cl::Hidden);
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}
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namespace {
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struct VISIBILITY_HIDDEN TwoAddressInstructionPass
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: public MachineFunctionPass {
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineRegisterInfo *MRI;
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LiveVariables *LV;
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public:
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static char ID; // Pass identification, replacement for typeid
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TwoAddressInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
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@ -57,6 +70,11 @@ namespace {
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/// runOnMachineFunction - pass entry point
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bool runOnMachineFunction(MachineFunction&);
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private:
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bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
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unsigned Reg,
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MachineBasicBlock::iterator OldPos);
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};
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char TwoAddressInstructionPass::ID = 0;
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@ -75,14 +93,113 @@ void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const {
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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/// Sink3AddrInstruction - A two-address instruction has been converted to a
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/// three-address instruction to avoid clobbering a register. Try to sink it
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/// past the instruction that would kill the above mentioned register to
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/// reduce register pressure.
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bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
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MachineInstr *MI, unsigned SavedReg,
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MachineBasicBlock::iterator OldPos) {
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// Check if it's safe to move this instruction.
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bool SeenStore = true; // Be conservative.
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if (!MI->isSafeToMove(TII, SeenStore))
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return false;
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unsigned DefReg = 0;
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SmallSet<unsigned, 4> UseRegs;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isRegister())
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continue;
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unsigned MOReg = MO.getReg();
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if (!MOReg)
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continue;
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if (MO.isUse() && MOReg != SavedReg)
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UseRegs.insert(MO.getReg());
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if (!MO.isDef())
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continue;
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if (MO.isImplicit())
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// Don't try to move it if it implicitly defines a register.
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return false;
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if (DefReg)
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// For now, don't move any instructions that define multiple registers.
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return false;
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DefReg = MO.getReg();
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}
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// Find the instruction that kills SavedReg.
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MachineInstr *KillMI = NULL;
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for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SavedReg),
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UE = MRI->use_end(); UI != UE; ++UI) {
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MachineOperand &UseMO = UI.getOperand();
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if (!UseMO.isKill())
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continue;
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KillMI = UseMO.getParent();
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break;
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}
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if (!KillMI || KillMI->getParent() != MBB)
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return false;
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// If any of the definitions are used by another instruction between
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// the position and the kill use, then it's not safe to sink it.
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// FIXME: This can be sped up if there is an easy way to query whether
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// an instruction if before or after another instruction. Then we can
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// use MachineRegisterInfo def / use instead.
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MachineOperand *KillMO = NULL;
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MachineBasicBlock::iterator KillPos = KillMI;
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++KillPos;
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for (MachineBasicBlock::iterator I = next(OldPos); I != KillPos; ++I) {
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MachineInstr *OtherMI = I;
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for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = OtherMI->getOperand(i);
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if (!MO.isRegister())
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continue;
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unsigned MOReg = MO.getReg();
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if (!MOReg)
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continue;
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if (DefReg == MOReg)
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return false;
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if (MO.isKill()) {
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if (OtherMI == KillMI && MOReg == SavedReg)
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// Save the operand that kills the register. We want unset the kill
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// marker is we can sink MI past it.
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KillMO = &MO;
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else if (UseRegs.count(MOReg))
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// One of the uses is killed before the destination.
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return false;
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}
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}
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}
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if (SinkLimit != -1 && Num3AddrSunk == (unsigned)SinkLimit)
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return false;
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// Update kill and LV information.
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KillMO->setIsKill(false);
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KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
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KillMO->setIsKill(true);
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LiveVariables::VarInfo& VarInfo = LV->getVarInfo(SavedReg);
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VarInfo.removeKill(KillMI);
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VarInfo.Kills.push_back(MI);
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// Move instruction to its destination.
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MBB->remove(MI);
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MBB->insert(KillPos, MI);
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++Num3AddrSunk;
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return true;
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}
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/// runOnMachineFunction - Reduce two-address instructions to two
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/// operands.
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///
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bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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DOUT << "Machine Function\n";
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const TargetMachine &TM = MF.getTarget();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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LiveVariables &LV = getAnalysis<LiveVariables>();
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MRI = &MF.getRegInfo();
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TII = TM.getInstrInfo();
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TRI = TM.getRegisterInfo();
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LV = &getAnalysis<LiveVariables>();
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bool MadeChange = false;
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@ -150,14 +267,14 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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unsigned regC = mi->getOperand(3-si).getReg();
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if (mi->killsRegister(regC)) {
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DOUT << "2addr: COMMUTING : " << *mi;
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MachineInstr *NewMI = TII.commuteInstruction(mi);
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MachineInstr *NewMI = TII->commuteInstruction(mi);
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if (NewMI == 0) {
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DOUT << "2addr: COMMUTING FAILED!\n";
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} else {
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DOUT << "2addr: COMMUTED TO: " << *NewMI;
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// If the instruction changed to commute it, update livevar.
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if (NewMI != mi) {
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LV.instructionChanged(mi, NewMI); // Update live variables
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LV->instructionChanged(mi, NewMI); // Update live variables
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mbbi->insert(mi, NewMI); // Insert the new inst
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mbbi->erase(mi); // Nuke the old inst.
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mi = NewMI;
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@ -180,11 +297,12 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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assert(TID.getOperandConstraint(i, TOI::TIED_TO) == -1);
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#endif
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if (MachineInstr *New = TII.convertToThreeAddress(mbbi, mi, LV)) {
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if (MachineInstr *New=TII->convertToThreeAddress(mbbi, mi, *LV)) {
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DOUT << "2addr: CONVERTING 2-ADDR: " << *mi;
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DOUT << "2addr: TO 3-ADDR: " << *New;
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bool Sunk = Sink3AddrInstruction(mbbi, New, regB, mi);
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mbbi->erase(mi); // Nuke the old inst.
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mi = New;
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if (!Sunk) mi = New;
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++NumConvertedTo3Addr;
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// Done with this instruction.
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break;
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@ -194,20 +312,20 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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InstructionRearranged:
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const TargetRegisterClass* rc = MF.getRegInfo().getRegClass(regA);
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TII.copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
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TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
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MachineBasicBlock::iterator prevMi = prior(mi);
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DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM));
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// update live variables for regB
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LiveVariables::VarInfo& varInfoB = LV.getVarInfo(regB);
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LiveVariables::VarInfo& varInfoB = LV->getVarInfo(regB);
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// regB is used in this BB.
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varInfoB.UsedBlocks[mbbi->getNumber()] = true;
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if (LV.removeVirtualRegisterKilled(regB, mbbi, mi))
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LV.addVirtualRegisterKilled(regB, prevMi);
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if (LV->removeVirtualRegisterKilled(regB, mbbi, mi))
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LV->addVirtualRegisterKilled(regB, prevMi);
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if (LV.removeVirtualRegisterDead(regB, mbbi, mi))
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LV.addVirtualRegisterDead(regB, prevMi);
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if (LV->removeVirtualRegisterDead(regB, mbbi, mi))
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LV->addVirtualRegisterDead(regB, prevMi);
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// replace all occurences of regB with regA
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for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
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@ -1,5 +1,5 @@
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; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86 -stats |& \
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; RUN: grep asm-printer | grep 14
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; RUN: grep asm-printer | grep 13
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void %_ZN9__gnu_cxx9hashtableISt4pairIKPKciES3_NS_4hashIS3_EESt10_Select1stIS5_E5eqstrSaIiEE14find_or_insertERKS5__cond_true456.i(sbyte* %tmp435.i, uint* %tmp449.i.out) {
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newFuncRoot:
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@ -0,0 +1,29 @@
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; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats |& grep {Number of 3-address instructions sunk}
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define void @t2(<2 x i64>* %vDct, <2 x i64>* %vYp, i8* %skiplist, <2 x i64> %a1) nounwind {
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entry:
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%tmp25 = bitcast <2 x i64> %a1 to <8 x i16> ; <<8 x i16>> [#uses=1]
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br label %bb
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bb: ; preds = %bb, %entry
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%skiplist_addr.0.rec = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
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%vYp_addr.0.rec = shl i32 %skiplist_addr.0.rec, 3 ; <i32> [#uses=3]
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%vDct_addr.0 = getelementptr <2 x i64>* %vDct, i32 %vYp_addr.0.rec ; <<2 x i64>*> [#uses=1]
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%vYp_addr.0 = getelementptr <2 x i64>* %vYp, i32 %vYp_addr.0.rec ; <<2 x i64>*> [#uses=1]
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%skiplist_addr.0 = getelementptr i8* %skiplist, i32 %skiplist_addr.0.rec ; <i8*> [#uses=1]
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%vDct_addr.0.sum43 = or i32 %vYp_addr.0.rec, 1 ; <i32> [#uses=1]
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%tmp7 = getelementptr <2 x i64>* %vDct, i32 %vDct_addr.0.sum43 ; <<2 x i64>*> [#uses=1]
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%tmp8 = load <2 x i64>* %tmp7, align 16 ; <<2 x i64>> [#uses=1]
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%tmp11 = load <2 x i64>* %vDct_addr.0, align 16 ; <<2 x i64>> [#uses=1]
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%tmp13 = bitcast <2 x i64> %tmp8 to <8 x i16> ; <<8 x i16>> [#uses=1]
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%tmp15 = bitcast <2 x i64> %tmp11 to <8 x i16> ; <<8 x i16>> [#uses=1]
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%tmp16 = shufflevector <8 x i16> %tmp15, <8 x i16> %tmp13, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x i16>> [#uses=1]
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%tmp26 = mul <8 x i16> %tmp25, %tmp16 ; <<8 x i16>> [#uses=1]
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%tmp27 = bitcast <8 x i16> %tmp26 to <2 x i64> ; <<2 x i64>> [#uses=1]
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store <2 x i64> %tmp27, <2 x i64>* %vYp_addr.0, align 16
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%tmp37 = load i8* %skiplist_addr.0, align 1 ; <i8> [#uses=1]
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%tmp38 = icmp eq i8 %tmp37, 0 ; <i1> [#uses=1]
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%indvar.next = add i32 %skiplist_addr.0.rec, 1 ; <i32> [#uses=1]
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br i1 %tmp38, label %return, label %bb
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return: ; preds = %bb
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ret void
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}
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