[AMDGPU] Update AMDGOUUsage.rst descriptions
- Improve description of XNACK ELF flag. - Rename all uses of wave to wavefront to be consistent. Differential Revision: https://reviews.llvm.org/D43983 llvm-svn: 326989
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Tony Tye
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@ -503,6 +503,11 @@ The AMDGPU backend uses the following ELF header:
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target feature is
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enabled for all code
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contained in the code object.
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If the processor
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does not support the
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``xnack`` target
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feature then must
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be 0.
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See
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:ref:`amdgpu-target-features`.
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================================= ========== =============================
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@ -1455,7 +1460,7 @@ address to physical address is:
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There are different ways that the wavefront scratch base address is determined
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by a wavefront (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). This
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memory can be accessed in an interleaved manner using buffer instruction with
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the scratch buffer descriptor and per wave scratch offset, by the scratch
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the scratch buffer descriptor and per wavefront scratch offset, by the scratch
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instructions, or by flat instructions. If each lane of a wavefront accesses the
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same private address, the interleaving results in adjacent dwords being accessed
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and hence requires fewer cache lines to be fetched. Multi-dword access is not
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@ -1796,7 +1801,7 @@ CP microcode requires the Kernel descritor to be allocated on 64 byte alignment.
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Bits Size Field Name Description
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======= ======= =============================== ===========================================================================
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0 1 bit ENABLE_SGPR_PRIVATE_SEGMENT Enable the setup of the
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_WAVE_OFFSET SGPR wave scratch offset
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_WAVEFRONT_OFFSET SGPR wavefront scratch offset
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system register (see
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:ref:`amdgpu-amdhsa-initial-kernel-execution-state`).
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@ -1883,7 +1888,7 @@ CP microcode requires the Kernel descritor to be allocated on 64 byte alignment.
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exceptions exceptions
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enabled which are generated
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when a memory violation has
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occurred for this wave from
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occurred for this wavefront from
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L1 or LDS
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(write-to-read-only-memory,
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mis-aligned atomic, LDS
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@ -2007,10 +2012,10 @@ SGPR0, the next enabled register is SGPR1 etc.; disabled registers do not have
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an SGPR number.
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The initial SGPRs comprise up to 16 User SRGPs that are set by CP and apply to
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all waves of the grid. It is possible to specify more than 16 User SGPRs using
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all wavefronts of the grid. It is possible to specify more than 16 User SGPRs using
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the ``enable_sgpr_*`` bit fields, in which case only the first 16 are actually
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initialized. These are then immediately followed by the System SGPRs that are
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set up by ADC/SPI and can have different values for each wave of the grid
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set up by ADC/SPI and can have different values for each wavefront of the grid
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dispatch.
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SGPR register initial state is defined in
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@ -2025,10 +2030,10 @@ SGPR register initial state is defined in
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field) SGPRs
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========== ========================== ====== ==============================
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First Private Segment Buffer 4 V# that can be used, together
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(enable_sgpr_private with Scratch Wave Offset as an
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_segment_buffer) offset, to access the private
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memory space using a segment
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address.
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(enable_sgpr_private with Scratch Wavefront Offset
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_segment_buffer) as an offset, to access the
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private memory space using a
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segment address.
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CP uses the value provided by
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the runtime.
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@ -2068,7 +2073,7 @@ SGPR register initial state is defined in
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address is
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``SH_HIDDEN_PRIVATE_BASE_VIMID``
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plus this offset.) The value
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of Scratch Wave Offset must
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of Scratch Wavefront Offset must
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be added to this offset by
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the kernel machine code,
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right shifted by 8, and
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@ -2078,13 +2083,13 @@ SGPR register initial state is defined in
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to SGPRn-4 on GFX7, and
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SGPRn-6 on GFX8 (where SGPRn
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is the highest numbered SGPR
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allocated to the wave).
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allocated to the wavefront).
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FLAT_SCRATCH_HI is
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multiplied by 256 (as it is
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in units of 256 bytes) and
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added to
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``SH_HIDDEN_PRIVATE_BASE_VIMID``
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to calculate the per wave
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to calculate the per wavefront
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FLAT SCRATCH BASE in flat
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memory instructions that
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access the scratch
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@ -2124,7 +2129,7 @@ SGPR register initial state is defined in
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divides it if there are
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multiple Shader Arrays each
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with its own SPI). The value
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of Scratch Wave Offset must
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of Scratch Wavefront Offset must
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be added by the kernel
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machine code and the result
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moved to the FLAT_SCRATCH
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@ -2193,12 +2198,12 @@ SGPR register initial state is defined in
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then Work-Group Id Z 1 32 bit work-group id in Z
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(enable_sgpr_workgroup_id dimension of grid for
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_Z) wavefront.
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then Work-Group Info 1 {first_wave, 14'b0000,
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then Work-Group Info 1 {first_wavefront, 14'b0000,
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(enable_sgpr_workgroup ordered_append_term[10:0],
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_info) threadgroup_size_in_waves[5:0]}
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then Scratch Wave Offset 1 32 bit byte offset from base
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_info) threadgroup_size_in_wavefronts[5:0]}
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then Scratch Wavefront Offset 1 32 bit byte offset from base
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(enable_sgpr_private of scratch base of queue
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_segment_wave_offset) executing the kernel
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_segment_wavefront_offset) executing the kernel
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dispatch. Must be used as an
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offset with Private
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segment address when using
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@ -2244,8 +2249,8 @@ The setting of registers is is done by GPU CP/ADC/SPI hardware as follows:
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registers.
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2. Work-group Id registers X, Y, Z are set by ADC which supports any
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combination including none.
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3. Scratch Wave Offset is set by SPI in a per wave basis which is why its value
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cannot included with the flat scratch init value which is per queue.
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3. Scratch Wavefront Offset is set by SPI in a per wavefront basis which is why
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its value cannot included with the flat scratch init value which is per queue.
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4. The VGPRs are set by SPI which only supports specifying either (X), (X, Y)
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or (X, Y, Z).
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@ -2293,7 +2298,7 @@ Flat Scratch
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If the kernel may use flat operations to access scratch memory, the prolog code
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must set up FLAT_SCRATCH register pair (FLAT_SCRATCH_LO/FLAT_SCRATCH_HI which
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are in SGPRn-4/SGPRn-3). Initialization uses Flat Scratch Init and Scratch Wave
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are in SGPRn-4/SGPRn-3). Initialization uses Flat Scratch Init and Scratch Wavefront
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Offset SGPR registers (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`):
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GFX6
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@ -2304,7 +2309,7 @@ GFX7-GFX8
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``SH_HIDDEN_PRIVATE_BASE_VIMID`` to the base of scratch backing memory
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being managed by SPI for the queue executing the kernel dispatch. This is
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the same value used in the Scratch Segment Buffer V# base address. The
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prolog must add the value of Scratch Wave Offset to get the wave's byte
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prolog must add the value of Scratch Wavefront Offset to get the wavefront's byte
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scratch backing memory offset from ``SH_HIDDEN_PRIVATE_BASE_VIMID``. Since
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FLAT_SCRATCH_LO is in units of 256 bytes, the offset must be right shifted
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by 8 before moving into FLAT_SCRATCH_LO.
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@ -2318,7 +2323,7 @@ GFX7-GFX8
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GFX9
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The Flat Scratch Init is the 64 bit address of the base of scratch backing
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memory being managed by SPI for the queue executing the kernel dispatch. The
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prolog must add the value of Scratch Wave Offset and moved to the FLAT_SCRATCH
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prolog must add the value of Scratch Wavefront Offset and moved to the FLAT_SCRATCH
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pair for use as the flat scratch base in flat memory instructions.
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.. _amdgpu-amdhsa-memory-model:
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@ -2384,12 +2389,12 @@ For GFX6-GFX9:
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global order and involve no caching. Completion is reported to a wavefront in
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execution order.
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* The LDS memory has multiple request queues shared by the SIMDs of a
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CU. Therefore, the LDS operations performed by different waves of a work-group
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CU. Therefore, the LDS operations performed by different wavefronts of a work-group
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can be reordered relative to each other, which can result in reordering the
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visibility of vector memory operations with respect to LDS operations of other
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wavefronts in the same work-group. A ``s_waitcnt lgkmcnt(0)`` is required to
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ensure synchronization between LDS operations and vector memory operations
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between waves of a work-group, but not between operations performed by the
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between wavefronts of a work-group, but not between operations performed by the
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same wavefront.
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* The vector memory operations are performed as wavefront wide operations and
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completion is reported to a wavefront in execution order. The exception is
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@ -2399,7 +2404,7 @@ For GFX6-GFX9:
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* The vector memory operations access a single vector L1 cache shared by all
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SIMDs a CU. Therefore, no special action is required for coherence between the
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lanes of a single wavefront, or for coherence between wavefronts in the same
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work-group. A ``buffer_wbinvl1_vol`` is required for coherence between waves
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work-group. A ``buffer_wbinvl1_vol`` is required for coherence between wavefronts
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executing in different work-groups as they may be executing on different CUs.
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* The scalar memory operations access a scalar L1 cache shared by all wavefronts
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on a group of CUs. The scalar and vector L1 caches are not coherent. However,
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@ -2410,7 +2415,7 @@ For GFX6-GFX9:
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* The L2 cache has independent channels to service disjoint ranges of virtual
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addresses.
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* Each CU has a separate request queue per channel. Therefore, the vector and
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scalar memory operations performed by waves executing in different work-groups
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scalar memory operations performed by wavefronts executing in different work-groups
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(which may be executing on different CUs) of an agent can be reordered
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relative to each other. A ``s_waitcnt vmcnt(0)`` is required to ensure
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synchronization between vector memory operations of different CUs. It ensures a
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@ -2460,7 +2465,7 @@ case the AMDGPU backend ensures the memory location used to spill is never
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accessed by vector memory operations at the same time. If scalar writes are used
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then a ``s_dcache_wb`` is inserted before the ``s_endpgm`` and before a function
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return since the locations may be used for vector memory instructions by a
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future wave that uses the same scratch area, or a function call that creates a
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future wavefront that uses the same scratch area, or a function call that creates a
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frame at the same address, respectively. There is no need for a ``s_dcache_inv``
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as all scalar writes are write-before-read in the same thread.
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