Revert "RegScavenging: Add scavengeRegisterBackwards()"
Reverting this commit for now as it seems to be causing failures on test-suite tests on the clang-ppc64le-linux-lnt bot. This reverts commit r276044. llvm-svn: 276068
This commit is contained in:
Matthias Braun
parent
b11642bf94
commit
5b9722d6c7
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@ -157,24 +157,12 @@ public:
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/// available and do the appropriate bookkeeping. SPAdj is the stack
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/// adjustment due to call frame, it's passed along to eliminateFrameIndex().
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/// Returns the scavenged register.
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/// This function performs worse if kill flags are incomplete, consider using
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/// scavengeRegisterBackwards() instead!
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unsigned scavengeRegister(const TargetRegisterClass *RegClass,
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MachineBasicBlock::iterator I, int SPAdj);
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unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
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return scavengeRegister(RegClass, MBBI, SPAdj);
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}
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/// Make a register of the specific register class available from the current
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/// position backwards to the place before \p To. If \p RestoreAfter is true
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/// this includes the instruction at the current position.
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/// SPAdj is the stack adjustment due to call frame, it's passed along to
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/// eliminateFrameIndex().
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/// Returns the scavenged register.
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unsigned scavengeRegisterBackwards(const TargetRegisterClass &RC,
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MachineBasicBlock::iterator To,
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bool RestoreAfter, int SPAdj);
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/// Tell the scavenger a register is used.
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void setRegUsed(unsigned Reg, LaneBitmask LaneMask = ~0u);
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private:
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@ -214,12 +202,6 @@ private:
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/// Mark live-in registers of basic block as used.
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void setLiveInsUsed(const MachineBasicBlock &MBB);
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/// Spill a register after position \p After and reload it before position
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/// \p UseMI.
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ScavengedInfo &spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj,
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MachineBasicBlock::iterator After,
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MachineBasicBlock::iterator &UseMI);
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};
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} // End llvm namespace
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@ -41,7 +41,6 @@
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <algorithm>
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#include <climits>
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using namespace llvm;
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@ -1147,55 +1146,6 @@ void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &Fn,
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}
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}
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/// Allocate a register for the virtual register \p VReg. The last use of
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/// \p VReg is around the current position of the register scavenger \p RS.
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/// \p ReserveAfter controls whether the scavenged register needs to be reserved
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/// after the current instruction, otherwise it will only be reserved before the
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/// current instruction.
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static unsigned scavengeVReg(MachineRegisterInfo &MRI, RegScavenger &RS,
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unsigned VReg, bool ReserveAfter) {
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#ifndef NDEBUG
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// Verify that all definitions and uses are in the same basic block.
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const MachineBasicBlock *CommonMBB = nullptr;
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bool HadDef = false;
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for (MachineOperand &MO : MRI.reg_nodbg_operands(VReg)) {
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MachineBasicBlock *MBB = MO.getParent()->getParent();
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if (CommonMBB == nullptr)
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CommonMBB = MBB;
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assert(MBB == CommonMBB && "All defs+uses must be in the same basic block");
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if (MO.isDef())
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HadDef = true;
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}
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assert(HadDef && "Must have at least 1 Def");
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#endif
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// We should only have one definition of the register. However to accomodate
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// the requirements of two address code we also allow definitions in
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// subsequent instructions provided they also read the register. That way
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// we get a single contiguous lifetime.
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//
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// Definitions in MRI.def_begin() are unordered, search for the first.
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const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
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MachineRegisterInfo::def_iterator FirstDef =
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std::find_if(MRI.def_begin(VReg), MRI.def_end(),
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[VReg, TRI](const MachineOperand &MO) {
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return !MO.getParent()->readsRegister(VReg, TRI);
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});
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assert(FirstDef != MRI.def_end() &&
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"Must have one definition that does not redefine vreg");
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MachineInstr &DefMI = *FirstDef->getParent();
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// The register scavenger will report a free register inserting an emergency
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// spill/reload if necessary.
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int SPAdj = 0;
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const TargetRegisterClass &RC = *MRI.getRegClass(VReg);
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unsigned SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(),
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ReserveAfter, SPAdj);
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MRI.replaceRegWith(VReg, SReg);
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++NumScavengedRegs;
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return SReg;
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}
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/// doScavengeFrameVirtualRegs - Replace all frame index virtual registers
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/// with physical registers. Use the register scavenger to find an
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/// appropriate register to use.
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@ -1208,46 +1158,77 @@ doScavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger *RS) {
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// Run through the instructions and find any virtual registers.
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MachineRegisterInfo &MRI = MF.getRegInfo();
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for (MachineBasicBlock &MBB : MF) {
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RS->enterBasicBlockEnd(MBB);
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RS->enterBasicBlock(MBB);
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bool LastIterationHadVRegUses = false;
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for (MachineBasicBlock::iterator I = MBB.end(); I != MBB.begin(); ) {
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--I;
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// Move RegScavenger to the position between *I and *std::next(I).
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RS->backward(I);
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int SPAdj = 0;
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// Look for unassigned vregs in the uses of *std::next(I).
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MachineBasicBlock::iterator N = std::next(I);
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if (LastIterationHadVRegUses) {
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const MachineInstr &NMI = *N;
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for (const MachineOperand &MO : NMI.operands()) {
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if (!MO.isReg() || !MO.readsReg())
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continue;
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unsigned Reg = MO.getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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unsigned SReg = scavengeVReg(MRI, *RS, Reg, true);
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RS->setRegUsed(SReg);
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}
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}
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}
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// The instruction stream may change in the loop, so check MBB.end()
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// directly.
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for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
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// We might end up here again with a NULL iterator if we scavenged a
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// register for which we inserted spill code for definition by what was
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// originally the first instruction in MBB.
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if (I == MachineBasicBlock::iterator(nullptr))
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I = MBB.begin();
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// Look for unassigned vregs in the defs of *I.
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LastIterationHadVRegUses = false;
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const MachineInstr &MI = *I;
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MachineBasicBlock::iterator J = std::next(I);
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MachineBasicBlock::iterator P =
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I == MBB.begin() ? MachineBasicBlock::iterator(nullptr)
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: std::prev(I);
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// RS should process this instruction before we might scavenge at this
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// location. This is because we might be replacing a virtual register
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// defined by this instruction, and if so, registers killed by this
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// instruction are available, and defined registers are not.
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RS->forward(I);
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for (const MachineOperand &MO : MI.operands()) {
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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continue;
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// We have to look at all operands anyway so we can precalculate here
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// whether there is a reading operand. This allows use to skip the use
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// step in the next iteration if there was none.
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if (MO.readsReg())
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LastIterationHadVRegUses = true;
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if (MO.isDef())
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scavengeVReg(MRI, *RS, Reg, false);
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// When we first encounter a new virtual register, it
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// must be a definition.
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assert(MO.isDef() && "frame index virtual missing def!");
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// Scavenge a new scratch register
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const TargetRegisterClass *RC = MRI.getRegClass(Reg);
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unsigned ScratchReg = RS->scavengeRegister(RC, J, SPAdj);
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++NumScavengedRegs;
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// Replace this reference to the virtual register with the
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// scratch register.
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assert(ScratchReg && "Missing scratch register!");
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MRI.replaceRegWith(Reg, ScratchReg);
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// Because this instruction was processed by the RS before this
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// register was allocated, make sure that the RS now records the
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// register as being used.
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RS->setRegUsed(ScratchReg);
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}
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// If the scavenger needed to use one of its spill slots, the
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// spill code will have been inserted in between I and J. This is a
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// problem because we need the spill code before I: Move I to just
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// prior to J.
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if (I != std::prev(J)) {
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MBB.splice(J, &MBB, I);
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// Before we move I, we need to prepare the RS to visit I again.
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// Specifically, RS will assert if it sees uses of registers that
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// it believes are undefined. Because we have already processed
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// register kills in I, when it visits I again, it will believe that
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// those registers are undefined. To avoid this situation, unprocess
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// the instruction I.
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assert(RS->getCurrentPosition() == I &&
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"The register scavenger has an unexpected position");
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I = P;
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RS->unprocess(P);
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} else
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++I;
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}
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}
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}
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@ -299,14 +299,6 @@ void RegScavenger::backward() {
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}
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}
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// Expire scavenge spill frameindex uses.
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for (ScavengedInfo &I : Scavenged) {
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if (I.Restore == &MI) {
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I.Reg = 0;
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I.Restore = nullptr;
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}
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}
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if (MBBI == MBB->begin()) {
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MBBI = MachineBasicBlock::iterator(nullptr);
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Tracking = false;
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@ -406,72 +398,6 @@ unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
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return Survivor;
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}
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static std::pair<unsigned, MachineBasicBlock::iterator>
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findSurvivorBackwards(const TargetRegisterInfo &TRI,
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MachineBasicBlock::iterator From, MachineBasicBlock::iterator To,
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BitVector &Available, BitVector &Candidates) {
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bool FoundTo = false;
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unsigned Survivor = 0;
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MachineBasicBlock::iterator Pos;
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MachineBasicBlock &MBB = *From->getParent();
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MachineBasicBlock::iterator I = From;
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unsigned InstrLimit = 25;
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unsigned InstrCountDown = InstrLimit;
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for (;;) {
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const MachineInstr &MI = *I;
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if (MI.isDebugValue())
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continue;
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// Remove any candidates touched by instruction.
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bool FoundVReg = false;
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for (const MachineOperand &MO : MI.operands()) {
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if (MO.isRegMask()) {
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Candidates.clearBitsNotInMask(MO.getRegMask());
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continue;
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}
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if (!MO.isReg() || MO.isUndef())
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continue;
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unsigned Reg = MO.getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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FoundVReg = true;
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} else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
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Candidates.reset(*AI);
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}
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}
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if (I == To) {
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// If one of the available registers survived this long take it.
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Available &= Candidates;
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int Reg = Available.find_first();
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if (Reg != -1)
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return std::make_pair(Reg, MBB.end());
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// Otherwise we will continue up to InstrLimit instructions to fine
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// the register which is not defined/used for the longest time.
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FoundTo = true;
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Pos = To;
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}
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if (FoundTo) {
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if (Survivor == 0 || !Candidates.test(Survivor)) {
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int Reg = Candidates.find_first();
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if (Reg == -1)
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break;
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Survivor = Reg;
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}
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if (--InstrCountDown == 0 || I == MBB.begin())
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break;
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if (FoundVReg) {
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// We found a vreg, reset the InstrLimit counter.
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InstrCountDown = InstrLimit;
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Pos = I;
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}
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}
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--I;
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}
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return std::make_pair(Survivor, Pos);
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}
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static unsigned getFrameIndexOperandNum(MachineInstr &MI) {
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unsigned i = 0;
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while (!MI.getOperand(i).isFI()) {
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@ -481,81 +407,6 @@ static unsigned getFrameIndexOperandNum(MachineInstr &MI) {
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return i;
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}
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RegScavenger::ScavengedInfo &
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RegScavenger::spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj,
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MachineBasicBlock::iterator Before,
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MachineBasicBlock::iterator &UseMI) {
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// Find an available scavenging slot with size and alignment matching
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// the requirements of the class RC.
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const MachineFunction &MF = *Before->getParent()->getParent();
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const MachineFrameInfo &MFI = *MF.getFrameInfo();
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unsigned NeedSize = RC.getSize();
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unsigned NeedAlign = RC.getAlignment();
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unsigned SI = Scavenged.size(), Diff = UINT_MAX;
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int FIB = MFI.getObjectIndexBegin(), FIE = MFI.getObjectIndexEnd();
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for (unsigned I = 0; I < Scavenged.size(); ++I) {
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if (Scavenged[I].Reg != 0)
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continue;
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// Verify that this slot is valid for this register.
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int FI = Scavenged[I].FrameIndex;
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if (FI < FIB || FI >= FIE)
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continue;
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unsigned S = MFI.getObjectSize(FI);
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unsigned A = MFI.getObjectAlignment(FI);
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if (NeedSize > S || NeedAlign > A)
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continue;
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// Avoid wasting slots with large size and/or large alignment. Pick one
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// that is the best fit for this register class (in street metric).
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// Picking a larger slot than necessary could happen if a slot for a
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// larger register is reserved before a slot for a smaller one. When
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// trying to spill a smaller register, the large slot would be found
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// first, thus making it impossible to spill the larger register later.
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unsigned D = (S-NeedSize) + (A-NeedAlign);
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if (D < Diff) {
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SI = I;
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Diff = D;
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}
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}
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if (SI == Scavenged.size()) {
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// We need to scavenge a register but have no spill slot, the target
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// must know how to do it (if not, we'll assert below).
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Scavenged.push_back(ScavengedInfo(FIE));
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}
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// Avoid infinite regress
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Scavenged[SI].Reg = Reg;
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// If the target knows how to save/restore the register, let it do so;
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// otherwise, use the emergency stack spill slot.
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if (!TRI->saveScavengerRegister(*MBB, Before, UseMI, &RC, Reg)) {
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// Spill the scavenged register before \p Before.
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int FI = Scavenged[SI].FrameIndex;
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if (FI < FIB || FI >= FIE) {
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std::string Msg = std::string("Error while trying to spill ") +
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TRI->getName(Reg) + " from class " + TRI->getRegClassName(&RC) +
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": Cannot scavenge register without an emergency spill slot!";
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report_fatal_error(Msg.c_str());
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}
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TII->storeRegToStackSlot(*MBB, Before, Reg, true, Scavenged[SI].FrameIndex,
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&RC, TRI);
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MachineBasicBlock::iterator II = std::prev(Before);
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unsigned FIOperandNum = getFrameIndexOperandNum(*II);
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TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
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// Restore the scavenged register before its use (or first terminator).
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TII->loadRegFromStackSlot(*MBB, UseMI, Reg, Scavenged[SI].FrameIndex,
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&RC, TRI);
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II = std::prev(UseMI);
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FIOperandNum = getFrameIndexOperandNum(*II);
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TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
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}
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return Scavenged[SI];
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}
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unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
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MachineBasicBlock::iterator I,
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int SPAdj) {
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@ -588,45 +439,81 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
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return SReg;
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}
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ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);
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Scavenged.Restore = std::prev(UseMI);
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// Find an available scavenging slot with size and alignment matching
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// the requirements of the class RC.
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const MachineFrameInfo &MFI = *MF.getFrameInfo();
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unsigned NeedSize = RC->getSize();
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unsigned NeedAlign = RC->getAlignment();
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unsigned SI = Scavenged.size(), Diff = UINT_MAX;
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int FIB = MFI.getObjectIndexBegin(), FIE = MFI.getObjectIndexEnd();
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for (unsigned I = 0; I < Scavenged.size(); ++I) {
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if (Scavenged[I].Reg != 0)
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continue;
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// Verify that this slot is valid for this register.
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int FI = Scavenged[I].FrameIndex;
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if (FI < FIB || FI >= FIE)
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continue;
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unsigned S = MFI.getObjectSize(FI);
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unsigned A = MFI.getObjectAlignment(FI);
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if (NeedSize > S || NeedAlign > A)
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continue;
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// Avoid wasting slots with large size and/or large alignment. Pick one
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// that is the best fit for this register class (in street metric).
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// Picking a larger slot than necessary could happen if a slot for a
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// larger register is reserved before a slot for a smaller one. When
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// trying to spill a smaller register, the large slot would be found
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// first, thus making it impossible to spill the larger register later.
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unsigned D = (S-NeedSize) + (A-NeedAlign);
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if (D < Diff) {
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SI = I;
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Diff = D;
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}
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}
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if (SI == Scavenged.size()) {
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// We need to scavenge a register but have no spill slot, the target
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// must know how to do it (if not, we'll assert below).
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Scavenged.push_back(ScavengedInfo(FIE));
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}
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// Avoid infinite regress
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Scavenged[SI].Reg = SReg;
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// If the target knows how to save/restore the register, let it do so;
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// otherwise, use the emergency stack spill slot.
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if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
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// Spill the scavenged register before I.
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int FI = Scavenged[SI].FrameIndex;
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if (FI < FIB || FI >= FIE) {
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std::string Msg = std::string("Error while trying to spill ") +
|
||||
TRI->getName(SReg) + " from class " + TRI->getRegClassName(RC) +
|
||||
": Cannot scavenge register without an emergency spill slot!";
|
||||
report_fatal_error(Msg.c_str());
|
||||
}
|
||||
TII->storeRegToStackSlot(*MBB, I, SReg, true, Scavenged[SI].FrameIndex,
|
||||
RC, TRI);
|
||||
MachineBasicBlock::iterator II = std::prev(I);
|
||||
|
||||
unsigned FIOperandNum = getFrameIndexOperandNum(*II);
|
||||
TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
|
||||
|
||||
// Restore the scavenged register before its use (or first terminator).
|
||||
TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex,
|
||||
RC, TRI);
|
||||
II = std::prev(UseMI);
|
||||
|
||||
FIOperandNum = getFrameIndexOperandNum(*II);
|
||||
TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
|
||||
}
|
||||
|
||||
Scavenged[SI].Restore = &*std::prev(UseMI);
|
||||
|
||||
// Doing this here leads to infinite regress.
|
||||
// Scavenged[SI].Reg = SReg;
|
||||
|
||||
DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<
|
||||
"\n");
|
||||
|
||||
return SReg;
|
||||
}
|
||||
|
||||
unsigned RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,
|
||||
MachineBasicBlock::iterator To,
|
||||
bool RestoreAfter, int SPAdj) {
|
||||
const MachineBasicBlock &MBB = *To->getParent();
|
||||
const MachineFunction &MF = *MBB.getParent();
|
||||
// Consider all allocatable registers in the register class initially
|
||||
BitVector Candidates = TRI->getAllocatableSet(MF, &RC);
|
||||
|
||||
// Try to find a register that's unused if there is one, as then we won't
|
||||
// have to spill.
|
||||
BitVector Available = getRegsAvailable(&RC);
|
||||
|
||||
// Find the register whose use is furthest away.
|
||||
MachineBasicBlock::iterator UseMI;
|
||||
std::pair<unsigned, MachineBasicBlock::iterator> P =
|
||||
findSurvivorBackwards(*TRI, MBBI, To, Available, Candidates);
|
||||
unsigned Reg = P.first;
|
||||
assert(Reg != 0 && "No register left to scavenge!");
|
||||
// Found an available register?
|
||||
if (!Available.test(Reg)) {
|
||||
MachineBasicBlock::iterator ReloadBefore =
|
||||
RestoreAfter ? std::next(MBBI) : MBBI;
|
||||
DEBUG(dbgs() << "Reload before: " << *ReloadBefore << '\n');
|
||||
ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, P.second, ReloadBefore);
|
||||
Scavenged.Restore = std::prev(P.second);
|
||||
addRegUnits(RegUnitsAvailable, Reg);
|
||||
DEBUG(dbgs() << "Scavenged register with spill: " << PrintReg(Reg, TRI)
|
||||
<< " until " << *P.second);
|
||||
} else {
|
||||
DEBUG(dbgs() << "Scavenged free register: " << PrintReg(Reg, TRI) << '\n');
|
||||
}
|
||||
return Reg;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -140,8 +140,8 @@ define void @stored_fi_to_global_2_small_objects(float* addrspace(1)* %ptr) #0 {
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}stored_fi_to_global_huge_frame_offset:
|
||||
; GCN-DAG: s_add_i32 [[BASE_1_OFF_0:s[0-9]+]], 0, 0x3ffc
|
||||
; GCN-DAG: v_mov_b32_e32 [[BASE_0:v[0-9]+]], 0{{$}}
|
||||
; GCN: s_add_i32 [[BASE_1_OFF_0:s[0-9]+]], 0, 0x3ffc
|
||||
; GCN: v_mov_b32_e32 [[BASE_0:v[0-9]+]], 0{{$}}
|
||||
; GCN: buffer_store_dword [[BASE_0]], v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen
|
||||
|
||||
; GCN: v_mov_b32_e32 [[V_BASE_1_OFF_0:v[0-9]+]], [[BASE_1_OFF_0]]
|
||||
|
|
|
|||
|
|
@ -1,62 +1,34 @@
|
|||
; RUN: llc -march=mipsel -O0 -relocation-model=pic < %s | FileCheck %s
|
||||
; Check that register scavenging spill slot is close to $fp.
|
||||
target triple="mipsel--"
|
||||
; RUN: llc -march=mipsel -O0 -relocation-model=pic < %s | FileCheck %s
|
||||
|
||||
@var = external global i32
|
||||
@ptrvar = external global i8*
|
||||
; CHECK: sw ${{.*}}, 8($sp)
|
||||
; CHECK: lw ${{.*}}, 8($sp)
|
||||
|
||||
; CHECK-LABEL: func:
|
||||
define void @func() {
|
||||
%space = alloca i32, align 4
|
||||
%stackspace = alloca[16384 x i32], align 4
|
||||
|
||||
; ensure stackspace is not optimized out
|
||||
%stackspace_casted = bitcast [16384 x i32]* %stackspace to i8*
|
||||
store volatile i8* %stackspace_casted, i8** @ptrvar
|
||||
|
||||
; Load values to increase register pressure.
|
||||
%v0 = load volatile i32, i32* @var
|
||||
%v1 = load volatile i32, i32* @var
|
||||
%v2 = load volatile i32, i32* @var
|
||||
%v3 = load volatile i32, i32* @var
|
||||
%v4 = load volatile i32, i32* @var
|
||||
%v5 = load volatile i32, i32* @var
|
||||
%v6 = load volatile i32, i32* @var
|
||||
%v7 = load volatile i32, i32* @var
|
||||
%v8 = load volatile i32, i32* @var
|
||||
%v9 = load volatile i32, i32* @var
|
||||
%v10 = load volatile i32, i32* @var
|
||||
%v11 = load volatile i32, i32* @var
|
||||
%v12 = load volatile i32, i32* @var
|
||||
%v13 = load volatile i32, i32* @var
|
||||
%v14 = load volatile i32, i32* @var
|
||||
%v15 = load volatile i32, i32* @var
|
||||
%v16 = load volatile i32, i32* @var
|
||||
|
||||
; Computing a stack-relative values needs an additional register.
|
||||
; We should get an emergency spill/reload for this.
|
||||
; CHECK: sw ${{.*}}, 0($sp)
|
||||
; CHECK: lw ${{.*}}, 0($sp)
|
||||
store volatile i32 %v0, i32* %space
|
||||
|
||||
; store values so they are used.
|
||||
store volatile i32 %v0, i32* @var
|
||||
store volatile i32 %v1, i32* @var
|
||||
store volatile i32 %v2, i32* @var
|
||||
store volatile i32 %v3, i32* @var
|
||||
store volatile i32 %v4, i32* @var
|
||||
store volatile i32 %v5, i32* @var
|
||||
store volatile i32 %v6, i32* @var
|
||||
store volatile i32 %v7, i32* @var
|
||||
store volatile i32 %v8, i32* @var
|
||||
store volatile i32 %v9, i32* @var
|
||||
store volatile i32 %v10, i32* @var
|
||||
store volatile i32 %v11, i32* @var
|
||||
store volatile i32 %v12, i32* @var
|
||||
store volatile i32 %v13, i32* @var
|
||||
store volatile i32 %v14, i32* @var
|
||||
store volatile i32 %v15, i32* @var
|
||||
store volatile i32 %v16, i32* @var
|
||||
|
||||
ret void
|
||||
define i32 @main(i32 signext %argc, i8** %argv) #0 {
|
||||
entry:
|
||||
%retval = alloca i32, align 4
|
||||
%argc.addr = alloca i32, align 4
|
||||
%argv.addr = alloca i8**, align 4
|
||||
%v0 = alloca <16 x i8>, align 16
|
||||
%.compoundliteral = alloca <16 x i8>, align 16
|
||||
%v1 = alloca <16 x i8>, align 16
|
||||
%.compoundliteral1 = alloca <16 x i8>, align 16
|
||||
%unused_variable = alloca [16384 x i32], align 4
|
||||
%result = alloca <16 x i8>, align 16
|
||||
store i32 0, i32* %retval
|
||||
store i32 %argc, i32* %argc.addr, align 4
|
||||
store i8** %argv, i8*** %argv.addr, align 4
|
||||
store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, <16 x i8>* %.compoundliteral
|
||||
%0 = load <16 x i8>, <16 x i8>* %.compoundliteral
|
||||
store <16 x i8> %0, <16 x i8>* %v0, align 16
|
||||
store <16 x i8> zeroinitializer, <16 x i8>* %.compoundliteral1
|
||||
%1 = load <16 x i8>, <16 x i8>* %.compoundliteral1
|
||||
store <16 x i8> %1, <16 x i8>* %v1, align 16
|
||||
%2 = load <16 x i8>, <16 x i8>* %v0, align 16
|
||||
%3 = load <16 x i8>, <16 x i8>* %v1, align 16
|
||||
%mul = mul <16 x i8> %2, %3
|
||||
store <16 x i8> %mul, <16 x i8>* %result, align 16
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
attributes #0 = { noinline "no-frame-pointer-elim"="true" }
|
||||
|
|
|
|||
|
|
@ -25,8 +25,8 @@ entry:
|
|||
|
||||
; CHECK-DAG: li [[REG1:[0-9]+]], -128
|
||||
; CHECK-DAG: neg [[REG2:[0-9]+]],
|
||||
; CHECK: and [[REG3:[0-9]+]], [[REG2]], [[REG1]]
|
||||
; CHECK: stdux {{[0-9]+}}, 1, [[REG3]]
|
||||
; CHECK: and [[REG1]], [[REG2]], [[REG1]]
|
||||
; CHECK: stdux {{[0-9]+}}, 1, [[REG1]]
|
||||
|
||||
; CHECK: blr
|
||||
|
||||
|
|
|
|||
|
|
@ -212,15 +212,15 @@ define void @f10(i32 *%vptr) {
|
|||
; CHECK-NOFP-LABEL: f10:
|
||||
; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
|
||||
; CHECK-NOFP: lay [[REGISTER]], 4096(%r15)
|
||||
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
|
||||
; CHECK-NOFP: mvhi 0([[REGISTER]]), 42
|
||||
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
|
||||
; CHECK-NOFP: br %r14
|
||||
;
|
||||
; CHECK-FP-LABEL: f10:
|
||||
; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
|
||||
; CHECK-FP: lay [[REGISTER]], 4096(%r11)
|
||||
; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
|
||||
; CHECK-FP: mvhi 0([[REGISTER]]), 42
|
||||
; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
|
||||
; CHECK-FP: br %r14
|
||||
%i0 = load volatile i32 , i32 *%vptr
|
||||
%i1 = load volatile i32 , i32 *%vptr
|
||||
|
|
@ -250,8 +250,8 @@ define void @f11(i32 *%vptr) {
|
|||
; CHECK-NOFP: stmg %r6, %r15,
|
||||
; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
|
||||
; CHECK-NOFP: lay [[REGISTER]], 4096(%r15)
|
||||
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
|
||||
; CHECK-NOFP: mvhi 0([[REGISTER]]), 42
|
||||
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
|
||||
; CHECK-NOFP: lmg %r6, %r15,
|
||||
; CHECK-NOFP: br %r14
|
||||
%i0 = load volatile i32 , i32 *%vptr
|
||||
|
|
|
|||
|
|
@ -234,16 +234,16 @@ define void @f10(i32 *%vptr) {
|
|||
; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
|
||||
; CHECK-NOFP: llilh [[REGISTER]], 8
|
||||
; CHECK-NOFP: agr [[REGISTER]], %r15
|
||||
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
|
||||
; CHECK-NOFP: mvi 0([[REGISTER]]), 42
|
||||
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
|
||||
; CHECK-NOFP: br %r14
|
||||
;
|
||||
; CHECK-FP-LABEL: f10:
|
||||
; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
|
||||
; CHECK-FP: llilh [[REGISTER]], 8
|
||||
; CHECK-FP: agr [[REGISTER]], %r11
|
||||
; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
|
||||
; CHECK-FP: mvi 0([[REGISTER]]), 42
|
||||
; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
|
||||
; CHECK-FP: br %r14
|
||||
%i0 = load volatile i32 , i32 *%vptr
|
||||
%i1 = load volatile i32 , i32 *%vptr
|
||||
|
|
@ -274,8 +274,8 @@ define void @f11(i32 *%vptr) {
|
|||
; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
|
||||
; CHECK-NOFP: llilh [[REGISTER]], 8
|
||||
; CHECK-NOFP: agr [[REGISTER]], %r15
|
||||
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
|
||||
; CHECK-NOFP: mvi 0([[REGISTER]]), 42
|
||||
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
|
||||
; CHECK-NOFP: lmg %r6, %r15,
|
||||
; CHECK-NOFP: br %r14
|
||||
%i0 = load volatile i32 , i32 *%vptr
|
||||
|
|
|
|||
|
|
@ -279,15 +279,15 @@ define void @f10(i32 *%vptr, double *%dst) {
|
|||
; CHECK-NOFP-LABEL: f10:
|
||||
; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
|
||||
; CHECK-NOFP: lghi [[REGISTER]], 4096
|
||||
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
|
||||
; CHECK-NOFP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r15)
|
||||
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
|
||||
; CHECK-NOFP: br %r14
|
||||
;
|
||||
; CHECK-FP-LABEL: f10:
|
||||
; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
|
||||
; CHECK-FP: lghi [[REGISTER]], 4096
|
||||
; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
|
||||
; CHECK-FP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r11)
|
||||
; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
|
||||
; CHECK-FP: br %r14
|
||||
%region1 = alloca [978 x float], align 8
|
||||
%region2 = alloca [978 x float], align 8
|
||||
|
|
|
|||
|
|
@ -223,15 +223,15 @@ define void @f10(i32 *%vptr, i8 %byte) {
|
|||
; CHECK-NOFP-LABEL: f10:
|
||||
; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
|
||||
; CHECK-NOFP: llilh [[REGISTER]], 8
|
||||
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
|
||||
; CHECK-NOFP: stc %r3, 0([[REGISTER]],%r15)
|
||||
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
|
||||
; CHECK-NOFP: br %r14
|
||||
;
|
||||
; CHECK-FP-LABEL: f10:
|
||||
; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
|
||||
; CHECK-FP: llilh [[REGISTER]], 8
|
||||
; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
|
||||
; CHECK-FP: stc %r3, 0([[REGISTER]],%r11)
|
||||
; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
|
||||
; CHECK-FP: br %r14
|
||||
%i0 = load volatile i32 , i32 *%vptr
|
||||
%i1 = load volatile i32 , i32 *%vptr
|
||||
|
|
@ -259,8 +259,8 @@ define void @f11(i32 *%vptr, i8 %byte) {
|
|||
; CHECK-NOFP: stmg %r6, %r15,
|
||||
; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
|
||||
; CHECK-NOFP: llilh [[REGISTER]], 8
|
||||
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
|
||||
; CHECK-NOFP: stc %r3, 0([[REGISTER]],%r15)
|
||||
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
|
||||
; CHECK-NOFP: lmg %r6, %r15,
|
||||
; CHECK-NOFP: br %r14
|
||||
;
|
||||
|
|
@ -268,8 +268,8 @@ define void @f11(i32 *%vptr, i8 %byte) {
|
|||
; CHECK-FP: stmg %r6, %r15,
|
||||
; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
|
||||
; CHECK-FP: llilh [[REGISTER]], 8
|
||||
; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
|
||||
; CHECK-FP: stc %r3, 8([[REGISTER]],%r11)
|
||||
; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
|
||||
; CHECK-FP: lmg %r6, %r15,
|
||||
; CHECK-FP: br %r14
|
||||
%i0 = load volatile i32 , i32 *%vptr
|
||||
|
|
|
|||
|
|
@ -46,8 +46,8 @@ define i32 @test3() {
|
|||
; CHECK-LABEL: test3:
|
||||
; CHECK: ldr [[TEMP:r[0-7]]],
|
||||
; CHECK: add sp, [[TEMP]]
|
||||
; CHECK: ldr [[TEMP2:r[0-7]]],
|
||||
; CHECK: add [[TEMP2]], sp
|
||||
; CHECK: ldr [[TEMP]],
|
||||
; CHECK: add [[TEMP]], sp
|
||||
; EABI: ldr [[TEMP:r[0-7]]],
|
||||
; EABI: add sp, [[TEMP]]
|
||||
; IOS: subs r4, r7, #4
|
||||
|
|
|
|||
Loading…
Reference in New Issue