replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

add support for vector undef 

llvm-svn: 26863
This commit is contained in:
Chris Lattner 2006-03-19 06:10:09 +00:00
parent 0a03f789c2
commit 5b595af956
1 changed files with 4 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -220,6 +220,8 @@ def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; $rD = IMPLICIT_DEF_F8",
[(set F8RC:$rD, (undef))]>;
def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; $rD = IMPLICIT_DEF_F4",
[(set F4RC:$rD, (undef))]>;
def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
[(set VRRC:$rD, (v4f32 (undef)))]>;
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
// scheduler into a branch sequence.
@ -1148,6 +1150,8 @@ def : Pat<(v4i32 (load xoaddr:$src)),
def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
(STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
// Same as above, but using a temporary. FIXME: implement temporaries :)
/*