Revert "Refactored ARMTargetInfo in order to use the API of llvm/lib/Support/TargetParser.cpp for extracting target specific information."
This reverts commit r241267. Tests were failing on the bots. llvm-svn: 241275
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@ -3996,14 +3996,8 @@ class ARMTargetInfo : public TargetInfo {
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FP_Neon
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} FPMath;
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unsigned ArchISA;
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unsigned ArchKind;
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unsigned ArchProfile;
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unsigned ArchVersion;
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unsigned FPU : 5;
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unsigned ShouldUseInlineAtomic : 1;
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unsigned IsAAPCS : 1;
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unsigned IsThumb : 1;
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unsigned HWDiv : 2;
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@ -4025,6 +4019,37 @@ class ARMTargetInfo : public TargetInfo {
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static const Builtin::Info BuiltinInfo[];
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static bool shouldUseInlineAtomic(const llvm::Triple &T) {
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StringRef ArchName = T.getArchName();
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if (T.getArch() == llvm::Triple::arm ||
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T.getArch() == llvm::Triple::armeb) {
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StringRef VersionStr;
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if (ArchName.startswith("armv"))
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VersionStr = ArchName.substr(4, 1);
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else if (ArchName.startswith("armebv"))
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VersionStr = ArchName.substr(6, 1);
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else
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return false;
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unsigned Version;
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if (VersionStr.getAsInteger(10, Version))
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return false;
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return Version >= 6;
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}
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assert(T.getArch() == llvm::Triple::thumb ||
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T.getArch() == llvm::Triple::thumbeb);
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StringRef VersionStr;
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if (ArchName.startswith("thumbv"))
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VersionStr = ArchName.substr(6, 1);
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else if (ArchName.startswith("thumbebv"))
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VersionStr = ArchName.substr(8, 1);
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else
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return false;
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unsigned Version;
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if (VersionStr.getAsInteger(10, Version))
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return false;
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return Version >= 7;
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}
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void setABIAAPCS() {
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IsAAPCS = true;
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@ -4123,28 +4148,6 @@ class ARMTargetInfo : public TargetInfo {
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// FIXME: Override "preferred align" for double and long long.
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}
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void setArchInfo(StringRef ArchName) {
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ArchISA = llvm::ARMTargetParser::parseArchISA(ArchName);
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ArchKind = llvm::ARMTargetParser::parseArch(ArchName);
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ArchProfile = llvm::ARMTargetParser::parseArchProfile(ArchName);
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ArchVersion = llvm::ARMTargetParser::parseArchVersion(ArchName);
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ShouldUseInlineAtomic = (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) ||
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(ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
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// Cortex M does not support 8 byte atomics, while general Thumb2 does.
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if (ArchProfile == llvm::ARM::PK_M) {
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MaxAtomicPromoteWidth = 32;
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if (ShouldUseInlineAtomic)
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MaxAtomicInlineWidth = 32;
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}
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else {
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MaxAtomicPromoteWidth = 64;
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if (ShouldUseInlineAtomic)
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MaxAtomicInlineWidth = 64;
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}
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}
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public:
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ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
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: TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
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@ -4160,21 +4163,12 @@ public:
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break;
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}
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// if subArch is not specified Arc Info is based on the default CPU
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if (Triple.getSubArch() == llvm::Triple::SubArchType::NoSubArch) {
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unsigned ArchKind = llvm::ARMTargetParser::parseCPUArch(CPU);
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setArchInfo(llvm::ARMTargetParser::getArchName(ArchKind));
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}
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else
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setArchInfo(Triple.getArchName());
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// {} in inline assembly are neon specifiers, not assembly variant
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// specifiers.
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NoAsmVariants = true;
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// FIXME: this should be updated also when calling setCPU
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// currently causes regressions
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IsThumb = (ArchISA == llvm::ARM::IK_THUMB);
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// FIXME: Should we just treat this as a feature?
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IsThumb = getTriple().getArchName().startswith("thumb");
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// FIXME: This duplicates code from the driver that sets the -target-abi
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// option - this code is used if -target-abi isn't passed and should
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@ -4219,6 +4213,11 @@ public:
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// ARM targets default to using the ARM C++ ABI.
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TheCXXABI.set(TargetCXXABI::GenericARM);
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// ARM has atomics up to 8 bytes
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MaxAtomicPromoteWidth = 64;
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if (shouldUseInlineAtomic(getTriple()))
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MaxAtomicInlineWidth = 64;
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// Do force alignment of members that follow zero length bitfields. If
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// the alignment of the zero-length bitfield is greater than the member
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// that follows it, `bar', `bar' will be aligned as the type of the
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@ -4248,6 +4247,11 @@ public:
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// FIXME: This should be based on Arch attributes, not CPU names.
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void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
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StringRef ArchName = getTriple().getArchName();
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unsigned ArchKind = llvm::ARMTargetParser::parseArch(ArchName);
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bool IsV8 = (ArchKind == llvm::ARM::AK_ARMV8A ||
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ArchKind == llvm::ARM::AK_ARMV8_1A);
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if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
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Features["vfp2"] = true;
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else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
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@ -4272,7 +4276,7 @@ public:
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Features["hwdiv-arm"] = true;
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Features["crc"] = true;
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Features["crypto"] = true;
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} else if (CPU == "cortex-r5" || CPU == "cortex-r7" || ArchVersion == 8) {
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} else if (CPU == "cortex-r5" || CPU == "cortex-r7" || IsV8) {
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Features["hwdiv"] = true;
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Features["hwdiv-arm"] = true;
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} else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" ||
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@ -4355,14 +4359,26 @@ public:
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.Case("hwdiv-arm", HWDiv & HWDivARM)
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.Default(false);
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}
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const char *getCPUAttr() const {
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const char *CPUAttr;
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const char *getCPUDefineSuffix(StringRef Name) const {
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if(Name == "generic") {
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auto subarch = getTriple().getSubArch();
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switch (subarch) {
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case llvm::Triple::SubArchType::ARMSubArch_v8_1a:
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return "8_1A";
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default:
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break;
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}
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}
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unsigned ArchKind = llvm::ARMTargetParser::parseCPUArch(Name);
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if (ArchKind == llvm::ARM::AK_INVALID)
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return "";
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// For most sub-arches, the build attribute CPU name is enough.
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// For Cortex variants, it's slightly different.
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switch(ArchKind) {
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default:
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CPUAttr = llvm::ARMTargetParser::getCPUAttr(ArchKind);
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return CPUAttr ? CPUAttr : "" ;
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return llvm::ARMTargetParser::getCPUAttr(ArchKind);
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case llvm::ARM::AK_ARMV6M:
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case llvm::ARM::AK_ARMV6SM:
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return "6M";
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@ -4382,8 +4398,23 @@ public:
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return "8_1A";
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}
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}
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const char *getCPUProfile() const {
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switch(ArchProfile) {
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const char *getCPUProfile(StringRef Name) const {
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if(Name == "generic") {
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auto subarch = getTriple().getSubArch();
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switch (subarch) {
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case llvm::Triple::SubArchType::ARMSubArch_v8_1a:
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return "A";
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default:
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break;
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}
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}
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unsigned CPUArch = llvm::ARMTargetParser::parseCPUArch(Name);
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if (CPUArch == llvm::ARM::AK_INVALID)
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return "";
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StringRef ArchName = llvm::ARMTargetParser::getArchName(CPUArch);
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switch(llvm::ARMTargetParser::parseArchProfile(ArchName)) {
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case llvm::ARM::PK_A:
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return "A";
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case llvm::ARM::PK_R:
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@ -4395,28 +4426,35 @@ public:
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}
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}
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bool setCPU(const std::string &Name) override {
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unsigned ArchKind = llvm::ARMTargetParser::parseCPUArch(Name);
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if (ArchKind == llvm::ARM::AK_INVALID)
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if (!getCPUDefineSuffix(Name))
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return false;
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setArchInfo(llvm::ARMTargetParser::getArchName(ArchKind));
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// Cortex M does not support 8 byte atomics, while general Thumb2 does.
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StringRef Profile = getCPUProfile(Name);
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if (Profile == "M" && MaxAtomicInlineWidth) {
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MaxAtomicPromoteWidth = 32;
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MaxAtomicInlineWidth = 32;
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}
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CPU = Name;
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return true;
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}
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bool setFPMath(StringRef Name) override;
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bool supportsThumb(StringRef CPUAttr) const {
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return CPUAttr.count('T') || ArchVersion >= 6;
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bool supportsThumb(StringRef ArchName, StringRef CPUArch,
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unsigned CPUArchVer) const {
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return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
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(CPUArch.find('M') != StringRef::npos);
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}
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bool supportsThumb2(StringRef CPUAttr) const {
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return CPUAttr.equals("6T2") || ArchVersion >= 7;
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bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
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unsigned CPUArchVer) const {
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// We check both CPUArchVer and ArchName because when only triple is
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// specified, the default CPU is arm1136j-s.
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return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
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ArchName.endswith("v8.1a") ||
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ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
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}
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void getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const override {
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StringRef CPUAttr = getCPUAttr();
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StringRef CPUProfile = getCPUProfile();
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// Target identification.
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Builder.defineMacro("__arm");
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Builder.defineMacro("__arm__");
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@ -4424,12 +4462,19 @@ public:
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// Target properties.
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Builder.defineMacro("__REGISTER_PREFIX__", "");
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Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
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StringRef CPUArch = getCPUDefineSuffix(CPU);
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unsigned int CPUArchVer;
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if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
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llvm_unreachable("Invalid char for architecture version number");
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Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
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// ACLE 6.4.1 ARM/Thumb instruction set architecture
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StringRef CPUProfile = getCPUProfile(CPU);
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StringRef ArchName = getTriple().getArchName();
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// __ARM_ARCH is defined as an integer value indicating the current ARM ISA
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Builder.defineMacro("__ARM_ARCH", std::to_string(ArchVersion));
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if (ArchVersion >= 8) {
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Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
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if (CPUArch[0] >= '8') {
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Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
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Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
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}
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@ -4443,9 +4488,9 @@ public:
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// __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
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// Thumb ISA (including v6-M). It is set to 2 if the core supports the
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// Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
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if (supportsThumb2(CPUAttr))
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if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
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Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
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else if (supportsThumb(CPUAttr))
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else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
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Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
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// __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
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@ -4470,7 +4515,7 @@ public:
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// FIXME: It's more complicated than this and we don't really support
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// interworking.
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// Windows on ARM does not "support" interworking
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if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows())
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if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
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Builder.defineMacro("__THUMB_INTERWORK__");
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if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
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@ -4493,7 +4538,7 @@ public:
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if (IsThumb) {
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Builder.defineMacro("__THUMBEL__");
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Builder.defineMacro("__thumb__");
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if (supportsThumb2(CPUAttr))
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if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
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Builder.defineMacro("__thumb2__");
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}
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if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
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@ -4516,7 +4561,7 @@ public:
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// the VFP define, hence the soft float and arch check. This is subtly
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// different from gcc, we follow the intent which was that it should be set
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// when Neon instructions are actually available.
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if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
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if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
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Builder.defineMacro("__ARM_NEON");
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Builder.defineMacro("__ARM_NEON__");
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}
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if (Crypto)
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Builder.defineMacro("__ARM_FEATURE_CRYPTO");
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if (ArchVersion >= 6 && CPUAttr != "6M") {
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if (CPUArchVer >= 6 && CPUArch != "6M") {
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
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}
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bool is5EOrAbove = (ArchVersion >= 6 ||
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(ArchVersion == 5 && CPUAttr.count('E')));
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// FIXME: We are not getting all 32-bit ARM architectures
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bool is32Bit = (!IsThumb || supportsThumb2(CPUAttr));
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if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUAttr == "7EM"))
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bool is5EOrAbove = (CPUArchVer >= 6 ||
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(CPUArchVer == 5 &&
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CPUArch.find('E') != StringRef::npos));
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bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer));
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if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM"))
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Builder.defineMacro("__ARM_FEATURE_DSP");
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}
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void getTargetBuiltins(const Builtin::Info *&Records,
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