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Change ScheduleDAG's DAG member from a reference to a pointer, to prepare 

for the possibility of scheduling without a SelectionDAG being present.

llvm-svn: 59263
This commit is contained in:
Dan Gohman 2008-11-13 21:21:28 +00:00
parent 60d10c3d2a
commit 5a390b974c
7 changed files with 50 additions and 50 deletions
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4
llvm/include/llvm/CodeGen/ScheduleDAG.h
View File

@ -239,7 +239,7 @@ namespace llvm {
class ScheduleDAG { class ScheduleDAG {
public: public:
SelectionDAG &DAG; // DAG of the current basic block SelectionDAG *DAG; // DAG of the current basic block
MachineBasicBlock *BB; // Current basic block MachineBasicBlock *BB; // Current basic block
const TargetMachine &TM; // Target processor const TargetMachine &TM; // Target processor
const TargetInstrInfo *TII; // Target instruction information const TargetInstrInfo *TII; // Target instruction information
@ -253,7 +253,7 @@ namespace llvm {
std::vector<SUnit> SUnits; // The scheduling units. std::vector<SUnit> SUnits; // The scheduling units.
SmallSet<SDNode*, 16> CommuteSet; // Nodes that should be commuted. SmallSet<SDNode*, 16> CommuteSet; // Nodes that should be commuted.
ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb, ScheduleDAG(SelectionDAG *dag, MachineBasicBlock *bb,
const TargetMachine &tm); const TargetMachine &tm);
virtual ~ScheduleDAG() {} virtual ~ScheduleDAG() {}

14
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -20,7 +20,7 @@
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
using namespace llvm; using namespace llvm;
ScheduleDAG::ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb, ScheduleDAG::ScheduleDAG(SelectionDAG *dag, MachineBasicBlock *bb,
const TargetMachine &tm) const TargetMachine &tm)
: DAG(dag), BB(bb), TM(tm), MRI(BB->getParent()->getRegInfo()) { : DAG(dag), BB(bb), TM(tm), MRI(BB->getParent()->getRegInfo()) {
TII = TM.getInstrInfo(); TII = TM.getInstrInfo();
@ -76,17 +76,17 @@ void ScheduleDAG::BuildSchedUnits() {
// Reserve entries in the vector for each of the SUnits we are creating. This // Reserve entries in the vector for each of the SUnits we are creating. This
// ensure that reallocation of the vector won't happen, so SUnit*'s won't get // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
// invalidated. // invalidated.
SUnits.reserve(DAG.allnodes_size()); SUnits.reserve(DAG->allnodes_size());
// During scheduling, the NodeId field of SDNode is used to map SDNodes // During scheduling, the NodeId field of SDNode is used to map SDNodes
// to their associated SUnits by holding SUnits table indices. A value // to their associated SUnits by holding SUnits table indices. A value
// of -1 means the SDNode does not yet have an associated SUnit. // of -1 means the SDNode does not yet have an associated SUnit.
for (SelectionDAG::allnodes_iterator NI = DAG.allnodes_begin(), for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
E = DAG.allnodes_end(); NI != E; ++NI) E = DAG->allnodes_end(); NI != E; ++NI)
NI->setNodeId(-1); NI->setNodeId(-1);
for (SelectionDAG::allnodes_iterator NI = DAG.allnodes_begin(), for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
E = DAG.allnodes_end(); NI != E; ++NI) { E = DAG->allnodes_end(); NI != E; ++NI) {
if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate. if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
continue; continue;
@ -376,7 +376,7 @@ unsigned ScheduleDAG::ComputeMemOperandsEnd(SDNode *Node) {
void ScheduleDAG::dumpSchedule() const { void ScheduleDAG::dumpSchedule() const {
for (unsigned i = 0, e = Sequence.size(); i != e; i++) { for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
if (SUnit *SU = Sequence[i]) if (SUnit *SU = Sequence[i])
SU->dump(&DAG); SU->dump(DAG);
else else
cerr << "**** NOOP ****\n"; cerr << "**** NOOP ****\n";
} }

4
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
View File

@ -260,7 +260,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
if (RC && VRC != RC) { if (RC && VRC != RC) {
cerr << "Register class of operand and regclass of use don't agree!\n"; cerr << "Register class of operand and regclass of use don't agree!\n";
cerr << "Operand = " << IIOpNum << "\n"; cerr << "Operand = " << IIOpNum << "\n";
cerr << "Op->Val = "; Op.getNode()->dump(&DAG); cerr << "\n"; cerr << "Op->Val = "; Op.getNode()->dump(DAG); cerr << "\n";
cerr << "MI = "; MI->print(cerr); cerr << "MI = "; MI->print(cerr);
cerr << "VReg = " << VReg << "\n"; cerr << "VReg = " << VReg << "\n";
cerr << "VReg RegClass size = " << VRC->getSize() cerr << "VReg RegClass size = " << VRC->getSize()
@ -540,7 +540,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
switch (Node->getOpcode()) { switch (Node->getOpcode()) {
default: default:
#ifndef NDEBUG #ifndef NDEBUG
Node->dump(&DAG); Node->dump(DAG);
#endif #endif
assert(0 && "This target-independent node should have been selected!"); assert(0 && "This target-independent node should have been selected!");
break; break;

24
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
View File

@ -71,7 +71,7 @@ private:
std::vector<unsigned> LiveRegCycles; std::vector<unsigned> LiveRegCycles;
public: public:
ScheduleDAGFast(SelectionDAG &dag, MachineBasicBlock *bb, ScheduleDAGFast(SelectionDAG *dag, MachineBasicBlock *bb,
const TargetMachine &tm) const TargetMachine &tm)
: ScheduleDAG(dag, bb, tm) {} : ScheduleDAG(dag, bb, tm) {}
@ -125,7 +125,7 @@ void ScheduleDAGFast::Schedule() {
BuildSchedUnits(); BuildSchedUnits();
DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
SUnits[su].dumpAll(&DAG)); SUnits[su].dumpAll(DAG));
// Execute the actual scheduling loop. // Execute the actual scheduling loop.
ListScheduleBottomUp(); ListScheduleBottomUp();
@ -150,7 +150,7 @@ void ScheduleDAGFast::ReleasePred(SUnit *PredSU, bool isChain,
#ifndef NDEBUG #ifndef NDEBUG
if (PredSU->NumSuccsLeft < 0) { if (PredSU->NumSuccsLeft < 0) {
cerr << "*** List scheduling failed! ***\n"; cerr << "*** List scheduling failed! ***\n";
PredSU->dump(&DAG); PredSU->dump(DAG);
cerr << " has been released too many times!\n"; cerr << " has been released too many times!\n";
assert(0); assert(0);
} }
@ -167,7 +167,7 @@ void ScheduleDAGFast::ReleasePred(SUnit *PredSU, bool isChain,
/// the Available queue. /// the Available queue.
void ScheduleDAGFast::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { void ScheduleDAGFast::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
DOUT << "*** Scheduling [" << CurCycle << "]: "; DOUT << "*** Scheduling [" << CurCycle << "]: ";
DEBUG(SU->dump(&DAG)); DEBUG(SU->dump(DAG));
SU->Cycle = CurCycle; SU->Cycle = CurCycle;
// Bottom up: release predecessors // Bottom up: release predecessors
@ -246,7 +246,7 @@ SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) {
if (TryUnfold) { if (TryUnfold) {
SmallVector<SDNode*, 2> NewNodes; SmallVector<SDNode*, 2> NewNodes;
if (!TII->unfoldMemoryOperand(DAG, N, NewNodes)) if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
return NULL; return NULL;
DOUT << "Unfolding SU # " << SU->NodeNum << "\n"; DOUT << "Unfolding SU # " << SU->NodeNum << "\n";
@ -257,9 +257,9 @@ SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) {
unsigned NumVals = N->getNumValues(); unsigned NumVals = N->getNumValues();
unsigned OldNumVals = SU->Node->getNumValues(); unsigned OldNumVals = SU->Node->getNumValues();
for (unsigned i = 0; i != NumVals; ++i) for (unsigned i = 0; i != NumVals; ++i)
DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, i), SDValue(N, i)); DAG->ReplaceAllUsesOfValueWith(SDValue(SU->Node, i), SDValue(N, i));
DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, OldNumVals-1), DAG->ReplaceAllUsesOfValueWith(SDValue(SU->Node, OldNumVals-1),
SDValue(LoadNode, 1)); SDValue(LoadNode, 1));
SUnit *NewSU = CreateNewSUnit(N); SUnit *NewSU = CreateNewSUnit(N);
assert(N->getNodeId() == -1 && "Node already inserted!"); assert(N->getNodeId() == -1 && "Node already inserted!");
@ -515,7 +515,7 @@ void ScheduleDAGFast::ListScheduleBottomUp() {
unsigned CurCycle = 0; unsigned CurCycle = 0;
// Add root to Available queue. // Add root to Available queue.
if (!SUnits.empty()) { if (!SUnits.empty()) {
SUnit *RootSU = &SUnits[DAG.getRoot().getNode()->getNodeId()]; SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()];
assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!"); assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!");
RootSU->isAvailable = true; RootSU->isAvailable = true;
AvailableQueue.push(RootSU); AvailableQueue.push(RootSU);
@ -625,14 +625,14 @@ void ScheduleDAGFast::ListScheduleBottomUp() {
} }
if (!AnyNotSched) if (!AnyNotSched)
cerr << "*** List scheduling failed! ***\n"; cerr << "*** List scheduling failed! ***\n";
SUnits[i].dump(&DAG); SUnits[i].dump(DAG);
cerr << "has not been scheduled!\n"; cerr << "has not been scheduled!\n";
AnyNotSched = true; AnyNotSched = true;
} }
if (SUnits[i].NumSuccsLeft != 0) { if (SUnits[i].NumSuccsLeft != 0) {
if (!AnyNotSched) if (!AnyNotSched)
cerr << "*** List scheduling failed! ***\n"; cerr << "*** List scheduling failed! ***\n";
SUnits[i].dump(&DAG); SUnits[i].dump(DAG);
cerr << "has successors left!\n"; cerr << "has successors left!\n";
AnyNotSched = true; AnyNotSched = true;
} }
@ -654,5 +654,5 @@ llvm::ScheduleDAG* llvm::createFastDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG, SelectionDAG *DAG,
const TargetMachine *TM, const TargetMachine *TM,
MachineBasicBlock *BB, bool) { MachineBasicBlock *BB, bool) {
return new ScheduleDAGFast(*DAG, BB, *TM); return new ScheduleDAGFast(DAG, BB, *TM);
} }

8
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
View File

@ -62,7 +62,7 @@ private:
HazardRecognizer *HazardRec; HazardRecognizer *HazardRec;
public: public:
ScheduleDAGList(SelectionDAG &dag, MachineBasicBlock *bb, ScheduleDAGList(SelectionDAG *dag, MachineBasicBlock *bb,
const TargetMachine &tm, const TargetMachine &tm,
SchedulingPriorityQueue *availqueue, SchedulingPriorityQueue *availqueue,
HazardRecognizer *HR) HazardRecognizer *HR)
@ -142,7 +142,7 @@ void ScheduleDAGList::ReleaseSucc(SUnit *SuccSU, bool isChain) {
/// the Available queue. /// the Available queue.
void ScheduleDAGList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { void ScheduleDAGList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
DOUT << "*** Scheduling [" << CurCycle << "]: "; DOUT << "*** Scheduling [" << CurCycle << "]: ";
DEBUG(SU->dump(&DAG)); DEBUG(SU->dump(DAG));
Sequence.push_back(SU); Sequence.push_back(SU);
SU->Cycle = CurCycle; SU->Cycle = CurCycle;
@ -264,7 +264,7 @@ void ScheduleDAGList::ListScheduleTopDown() {
if (SUnits[i].NumPredsLeft != 0) { if (SUnits[i].NumPredsLeft != 0) {
if (!AnyNotSched) if (!AnyNotSched)
cerr << "*** List scheduling failed! ***\n"; cerr << "*** List scheduling failed! ***\n";
SUnits[i].dump(&DAG); SUnits[i].dump(DAG);
cerr << "has not been scheduled!\n"; cerr << "has not been scheduled!\n";
AnyNotSched = true; AnyNotSched = true;
} }
@ -543,7 +543,7 @@ ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG, SelectionDAG *DAG,
const TargetMachine *TM, const TargetMachine *TM,
MachineBasicBlock *BB, bool Fast) { MachineBasicBlock *BB, bool Fast) {
return new ScheduleDAGList(*DAG, BB, *TM, return new ScheduleDAGList(DAG, BB, *TM,
new LatencyPriorityQueue(), new LatencyPriorityQueue(),
IS->CreateTargetHazardRecognizer()); IS->CreateTargetHazardRecognizer());
} }

38
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -74,7 +74,7 @@ private:
std::vector<unsigned> LiveRegCycles; std::vector<unsigned> LiveRegCycles;
public: public:
ScheduleDAGRRList(SelectionDAG &dag, MachineBasicBlock *bb, ScheduleDAGRRList(SelectionDAG *dag, MachineBasicBlock *bb,
const TargetMachine &tm, bool isbottomup, bool f, const TargetMachine &tm, bool isbottomup, bool f,
SchedulingPriorityQueue *availqueue) SchedulingPriorityQueue *availqueue)
: ScheduleDAG(dag, bb, tm), isBottomUp(isbottomup), Fast(f), : ScheduleDAG(dag, bb, tm), isBottomUp(isbottomup), Fast(f),
@ -186,7 +186,7 @@ void ScheduleDAGRRList::Schedule() {
BuildSchedUnits(); BuildSchedUnits();
DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
SUnits[su].dumpAll(&DAG)); SUnits[su].dumpAll(DAG));
if (!Fast) { if (!Fast) {
CalculateDepths(); CalculateDepths();
CalculateHeights(); CalculateHeights();
@ -278,7 +278,7 @@ void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain,
#ifndef NDEBUG #ifndef NDEBUG
if (PredSU->NumSuccsLeft < 0) { if (PredSU->NumSuccsLeft < 0) {
cerr << "*** List scheduling failed! ***\n"; cerr << "*** List scheduling failed! ***\n";
PredSU->dump(&DAG); PredSU->dump(DAG);
cerr << " has been released too many times!\n"; cerr << " has been released too many times!\n";
assert(0); assert(0);
} }
@ -295,7 +295,7 @@ void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain,
/// the Available queue. /// the Available queue.
void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
DOUT << "*** Scheduling [" << CurCycle << "]: "; DOUT << "*** Scheduling [" << CurCycle << "]: ";
DEBUG(SU->dump(&DAG)); DEBUG(SU->dump(DAG));
SU->Cycle = CurCycle; SU->Cycle = CurCycle;
AvailableQueue->ScheduledNode(SU); AvailableQueue->ScheduledNode(SU);
@ -362,7 +362,7 @@ void ScheduleDAGRRList::CapturePred(SUnit *PredSU, SUnit *SU, bool isChain) {
/// its predecessor states to reflect the change. /// its predecessor states to reflect the change.
void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
DOUT << "*** Unscheduling [" << SU->Cycle << "]: "; DOUT << "*** Unscheduling [" << SU->Cycle << "]: ";
DEBUG(SU->dump(&DAG)); DEBUG(SU->dump(DAG));
AvailableQueue->UnscheduledNode(SU); AvailableQueue->UnscheduledNode(SU);
@ -651,7 +651,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
if (TryUnfold) { if (TryUnfold) {
SmallVector<SDNode*, 2> NewNodes; SmallVector<SDNode*, 2> NewNodes;
if (!TII->unfoldMemoryOperand(DAG, N, NewNodes)) if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
return NULL; return NULL;
DOUT << "Unfolding SU # " << SU->NodeNum << "\n"; DOUT << "Unfolding SU # " << SU->NodeNum << "\n";
@ -662,9 +662,9 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
unsigned NumVals = N->getNumValues(); unsigned NumVals = N->getNumValues();
unsigned OldNumVals = SU->Node->getNumValues(); unsigned OldNumVals = SU->Node->getNumValues();
for (unsigned i = 0; i != NumVals; ++i) for (unsigned i = 0; i != NumVals; ++i)
DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, i), SDValue(N, i)); DAG->ReplaceAllUsesOfValueWith(SDValue(SU->Node, i), SDValue(N, i));
DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, OldNumVals-1), DAG->ReplaceAllUsesOfValueWith(SDValue(SU->Node, OldNumVals-1),
SDValue(LoadNode, 1)); SDValue(LoadNode, 1));
// LoadNode may already exist. This can happen when there is another // LoadNode may already exist. This can happen when there is another
// load from the same location and producing the same type of value // load from the same location and producing the same type of value
@ -933,7 +933,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
unsigned CurCycle = 0; unsigned CurCycle = 0;
// Add root to Available queue. // Add root to Available queue.
if (!SUnits.empty()) { if (!SUnits.empty()) {
SUnit *RootSU = &SUnits[DAG.getRoot().getNode()->getNodeId()]; SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()];
assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!"); assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!");
RootSU->isAvailable = true; RootSU->isAvailable = true;
AvailableQueue->push(RootSU); AvailableQueue->push(RootSU);
@ -1079,14 +1079,14 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
} }
if (!AnyNotSched) if (!AnyNotSched)
cerr << "*** List scheduling failed! ***\n"; cerr << "*** List scheduling failed! ***\n";
SUnits[i].dump(&DAG); SUnits[i].dump(DAG);
cerr << "has not been scheduled!\n"; cerr << "has not been scheduled!\n";
AnyNotSched = true; AnyNotSched = true;
} }
if (SUnits[i].NumSuccsLeft != 0) { if (SUnits[i].NumSuccsLeft != 0) {
if (!AnyNotSched) if (!AnyNotSched)
cerr << "*** List scheduling failed! ***\n"; cerr << "*** List scheduling failed! ***\n";
SUnits[i].dump(&DAG); SUnits[i].dump(DAG);
cerr << "has successors left!\n"; cerr << "has successors left!\n";
AnyNotSched = true; AnyNotSched = true;
} }
@ -1119,7 +1119,7 @@ void ScheduleDAGRRList::ReleaseSucc(SUnit *SuccSU, bool isChain,
#ifndef NDEBUG #ifndef NDEBUG
if (SuccSU->NumPredsLeft < 0) { if (SuccSU->NumPredsLeft < 0) {
cerr << "*** List scheduling failed! ***\n"; cerr << "*** List scheduling failed! ***\n";
SuccSU->dump(&DAG); SuccSU->dump(DAG);
cerr << " has been released too many times!\n"; cerr << " has been released too many times!\n";
assert(0); assert(0);
} }
@ -1137,7 +1137,7 @@ void ScheduleDAGRRList::ReleaseSucc(SUnit *SuccSU, bool isChain,
/// the Available queue. /// the Available queue.
void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
DOUT << "*** Scheduling [" << CurCycle << "]: "; DOUT << "*** Scheduling [" << CurCycle << "]: ";
DEBUG(SU->dump(&DAG)); DEBUG(SU->dump(DAG));
SU->Cycle = CurCycle; SU->Cycle = CurCycle;
AvailableQueue->ScheduledNode(SU); AvailableQueue->ScheduledNode(SU);
@ -1201,14 +1201,14 @@ void ScheduleDAGRRList::ListScheduleTopDown() {
} }
if (!AnyNotSched) if (!AnyNotSched)
cerr << "*** List scheduling failed! ***\n"; cerr << "*** List scheduling failed! ***\n";
SUnits[i].dump(&DAG); SUnits[i].dump(DAG);
cerr << "has not been scheduled!\n"; cerr << "has not been scheduled!\n";
AnyNotSched = true; AnyNotSched = true;
} }
if (SUnits[i].NumPredsLeft != 0) { if (SUnits[i].NumPredsLeft != 0) {
if (!AnyNotSched) if (!AnyNotSched)
cerr << "*** List scheduling failed! ***\n"; cerr << "*** List scheduling failed! ***\n";
SUnits[i].dump(&DAG); SUnits[i].dump(DAG);
cerr << "has predecessors left!\n"; cerr << "has predecessors left!\n";
AnyNotSched = true; AnyNotSched = true;
} }
@ -1885,7 +1885,7 @@ llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
MachineBasicBlock *BB, MachineBasicBlock *BB,
bool Fast) { bool Fast) {
if (Fast) if (Fast)
return new ScheduleDAGRRList(*DAG, BB, *TM, true, true, return new ScheduleDAGRRList(DAG, BB, *TM, true, true,
new BURegReductionFastPriorityQueue()); new BURegReductionFastPriorityQueue());
const TargetInstrInfo *TII = TM->getInstrInfo(); const TargetInstrInfo *TII = TM->getInstrInfo();
@ -1894,7 +1894,7 @@ llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
BURegReductionPriorityQueue *PQ = new BURegReductionPriorityQueue(TII, TRI); BURegReductionPriorityQueue *PQ = new BURegReductionPriorityQueue(TII, TRI);
ScheduleDAGRRList *SD = ScheduleDAGRRList *SD =
new ScheduleDAGRRList(*DAG, BB, *TM, true, false, PQ); new ScheduleDAGRRList(DAG, BB, *TM, true, false, PQ);
PQ->setScheduleDAG(SD); PQ->setScheduleDAG(SD);
return SD; return SD;
} }
@ -1904,6 +1904,6 @@ llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
const TargetMachine *TM, const TargetMachine *TM,
MachineBasicBlock *BB, MachineBasicBlock *BB,
bool Fast) { bool Fast) {
return new ScheduleDAGRRList(*DAG, BB, *TM, false, Fast, return new ScheduleDAGRRList(DAG, BB, *TM, false, Fast,
new TDRegReductionPriorityQueue()); new TDRegReductionPriorityQueue());
} }

8
llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
View File

@ -387,7 +387,7 @@ namespace llvm {
template<> template<>
struct DOTGraphTraits<ScheduleDAG*> : public DefaultDOTGraphTraits { struct DOTGraphTraits<ScheduleDAG*> : public DefaultDOTGraphTraits {
static std::string getGraphName(const ScheduleDAG *G) { static std::string getGraphName(const ScheduleDAG *G) {
return DOTGraphTraits<SelectionDAG*>::getGraphName(&G->DAG); return DOTGraphTraits<SelectionDAG*>::getGraphName(G->DAG);
} }
static bool renderGraphFromBottomUp() { static bool renderGraphFromBottomUp() {
@ -421,7 +421,7 @@ namespace llvm {
static void addCustomGraphFeatures(ScheduleDAG *G, static void addCustomGraphFeatures(ScheduleDAG *G,
GraphWriter<ScheduleDAG*> &GW) { GraphWriter<ScheduleDAG*> &GW) {
GW.emitSimpleNode(0, "plaintext=circle", "GraphRoot"); GW.emitSimpleNode(0, "plaintext=circle", "GraphRoot");
const SDNode *N = G->DAG.getRoot().getNode(); const SDNode *N = G->DAG->getRoot().getNode();
if (N && N->getNodeId() != -1) if (N && N->getNodeId() != -1)
GW.emitEdge(0, -1, &G->SUnits[N->getNodeId()], -1, GW.emitEdge(0, -1, &G->SUnits[N->getNodeId()], -1,
"color=blue,style=dashed"); "color=blue,style=dashed");
@ -435,11 +435,11 @@ std::string DOTGraphTraits<ScheduleDAG*>::getNodeLabel(const SUnit *SU,
for (unsigned i = 0; i < SU->FlaggedNodes.size(); ++i) { for (unsigned i = 0; i < SU->FlaggedNodes.size(); ++i) {
Op += DOTGraphTraits<SelectionDAG*>::getNodeLabel(SU->FlaggedNodes[i], Op += DOTGraphTraits<SelectionDAG*>::getNodeLabel(SU->FlaggedNodes[i],
&G->DAG) + "\n"; G->DAG) + "\n";
} }
if (SU->Node) if (SU->Node)
Op += DOTGraphTraits<SelectionDAG*>::getNodeLabel(SU->Node, &G->DAG); Op += DOTGraphTraits<SelectionDAG*>::getNodeLabel(SU->Node, G->DAG);
else else
Op += "<CROSS RC COPY>"; Op += "<CROSS RC COPY>";