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Fix PR3826 - InstComb assert with vector shift, by not calling ComputeNumSignBits on a vector. 

llvm-svn: 67211
This commit is contained in:
Chris Lattner 2009-03-18 16:32:19 +00:00
parent ab8022055a
commit 595923ff75
2 changed files with 19 additions and 7 deletions
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15
llvm/lib/Transforms/Scalar/InstructionCombining.cpp
View File

@ -7029,15 +7029,16 @@ Instruction *InstCombiner::visitAShr(BinaryOperator &I) {
return ReplaceInstUsesWith(I, CSI);
// See if we can turn a signed shr into an unsigned shr.
if (!isa<VectorType>(I.getType()) &&
MaskedValueIsZero(Op0,
if (!isa<VectorType>(I.getType())) {
if (MaskedValueIsZero(Op0,
APInt::getSignBit(I.getType()->getPrimitiveSizeInBits())))
return BinaryOperator::CreateLShr(Op0, I.getOperand(1));
return BinaryOperator::CreateLShr(Op0, I.getOperand(1));
// Arithmetic shifting an all-sign-bit value is a no-op.
unsigned NumSignBits = ComputeNumSignBits(Op0);
if (NumSignBits == Op0->getType()->getPrimitiveSizeInBits())
return ReplaceInstUsesWith(I, Op0);
// Arithmetic shifting an all-sign-bit value is a no-op.
unsigned NumSignBits = ComputeNumSignBits(Op0);
if (NumSignBits == Op0->getType()->getPrimitiveSizeInBits())
return ReplaceInstUsesWith(I, Op0);
}
return 0;
}

11
llvm/test/Transforms/InstCombine/2009-03-18-vector-ashr-crash.ll Normal file
View File

@ -0,0 +1,11 @@
; RUN: llvm-as < %s | opt -instcombine | llvm-dis
; PR3826
define void @0(<4 x i16>*, <4 x i16>*) {
%3 = alloca <4 x i16>* ; <<4 x i16>**> [#uses=1]
%4 = load <4 x i16>* null, align 1 ; <<4 x i16>> [#uses=1]
%5 = ashr <4 x i16> %4, <i16 5, i16 5, i16 5, i16 5> ; <<4 x i16>> [#uses=1]
%6 = load <4 x i16>** %3 ; <<4 x i16>*> [#uses=1]
store <4 x i16> %5, <4 x i16>* %6, align 1
ret void
}