Test commit

llvm-svn: 288036
2016-11-28 15:33:03 +00:00 · 2016-11-28 15:33:03 +00:00 · 59168e28e0
parent a413361798
commit 59168e28e0
1 changed files with 0 additions and 1 deletions
--- a/llvm/lib/Target/Sparc/SparcRegisterInfo.td
+++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.td
@ -331,7 +331,6 @@ def IntRegs : RegisterClass<"SP", [i32, i64], 32,
                                 (sequence "L%u", 0, 7),
                                 (sequence "O%u", 0, 7))>;

-
 // Should be in the same order as IntRegs.
 def IntPair : RegisterClass<"SP", [v2i32], 64,
    (add I0_I1, I2_I3, I4_I5, I6_I7,