From 589cb004dee799a097b878a8a13e4ba43114d5bd Mon Sep 17 00:00:00 2001 From: Andrea Di Biagio Date: Thu, 22 Aug 2019 13:32:17 +0000 Subject: [PATCH] [MCA] consistently use MCPhysReg instead of unsigned as register type. NFCI llvm-svn: 369648 --- .../llvm/MCA/HardwareUnits/RegisterFile.h | 2 +- llvm/include/llvm/MCA/Instruction.h | 23 ++++++++++--------- llvm/lib/MCA/HardwareUnits/RegisterFile.cpp | 16 ++++++------- llvm/lib/MCA/InstrBuilder.cpp | 10 ++++---- llvm/lib/MCA/Instruction.cpp | 4 ++-- llvm/lib/MCA/Stages/DispatchStage.cpp | 2 +- 6 files changed, 28 insertions(+), 29 deletions(-) diff --git a/llvm/include/llvm/MCA/HardwareUnits/RegisterFile.h b/llvm/include/llvm/MCA/HardwareUnits/RegisterFile.h index 36506327bd29..cd7718d98744 100644 --- a/llvm/include/llvm/MCA/HardwareUnits/RegisterFile.h +++ b/llvm/include/llvm/MCA/HardwareUnits/RegisterFile.h @@ -220,7 +220,7 @@ public: // // Current implementation can simulate up to 32 register files (including the // special register file at index #0). - unsigned isAvailable(ArrayRef Regs) const; + unsigned isAvailable(ArrayRef Regs) const; // Returns the number of PRFs implemented by this processor. unsigned getNumRegisterFiles() const { return RegisterFiles.size(); } diff --git a/llvm/include/llvm/MCA/Instruction.h b/llvm/include/llvm/MCA/Instruction.h index 572c3bac0f7c..c97cb463d0f5 100644 --- a/llvm/include/llvm/MCA/Instruction.h +++ b/llvm/include/llvm/MCA/Instruction.h @@ -18,6 +18,7 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/MC/MCRegister.h" // definition of MCPhysReg. #include "llvm/Support/MathExtras.h" #ifndef NDEBUG @@ -42,7 +43,7 @@ struct WriteDescriptor { unsigned Latency; // This field is set to a value different than zero only if this // is an implicit definition. - unsigned RegisterID; + MCPhysReg RegisterID; // Instruction itineraries would set this field to the SchedClass ID. // Otherwise, it defaults to the WriteResourceID from the MCWriteLatencyEntry // element associated to this write. @@ -70,7 +71,7 @@ struct ReadDescriptor { // uses always come first in the sequence of uses. unsigned UseIndex; // This field is only set if this is an implicit read. - unsigned RegisterID; + MCPhysReg RegisterID; // Scheduling Class Index. It is used to query the scheduling model for the // MCSchedClassDesc object. unsigned SchedClassID; @@ -85,7 +86,7 @@ class ReadState; /// Field RegID is set to the invalid register for memory dependencies. struct CriticalDependency { unsigned IID; - unsigned RegID; + MCPhysReg RegID; unsigned Cycles; }; @@ -106,7 +107,7 @@ class WriteState { // to speedup queries on the register file. // For implicit writes, this field always matches the value of // field RegisterID from WD. - unsigned RegisterID; + MCPhysReg RegisterID; // Physical register file that serves register RegisterID. unsigned PRFID; @@ -146,7 +147,7 @@ class WriteState { SmallVector, 4> Users; public: - WriteState(const WriteDescriptor &Desc, unsigned RegID, + WriteState(const WriteDescriptor &Desc, MCPhysReg RegID, bool clearsSuperRegs = false, bool writesZero = false) : WD(&Desc), CyclesLeft(UNKNOWN_CYCLES), RegisterID(RegID), PRFID(0), ClearsSuperRegs(clearsSuperRegs), WritesZero(writesZero), @@ -158,7 +159,7 @@ public: int getCyclesLeft() const { return CyclesLeft; } unsigned getWriteResourceID() const { return WD->SClassOrWriteResourceID; } - unsigned getRegisterID() const { return RegisterID; } + MCPhysReg getRegisterID() const { return RegisterID; } unsigned getRegisterFileID() const { return PRFID; } unsigned getLatency() const { return WD->Latency; } unsigned getDependentWriteCyclesLeft() const { @@ -200,7 +201,7 @@ public: } void setDependentWrite(const WriteState *Other) { DependentWrite = Other; } - void writeStartEvent(unsigned IID, unsigned RegID, unsigned Cycles); + void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles); void setWriteZero() { WritesZero = true; } void setEliminated() { assert(Users.empty() && "Write is in an inconsistent state."); @@ -226,7 +227,7 @@ public: class ReadState { const ReadDescriptor *RD; // Physical register identified associated to this read. - unsigned RegisterID; + MCPhysReg RegisterID; // Physical register file that serves register RegisterID. unsigned PRFID; // Number of writes that contribute to the definition of RegisterID. @@ -253,14 +254,14 @@ class ReadState { bool IndependentFromDef; public: - ReadState(const ReadDescriptor &Desc, unsigned RegID) + ReadState(const ReadDescriptor &Desc, MCPhysReg RegID) : RD(&Desc), RegisterID(RegID), PRFID(0), DependentWrites(0), CyclesLeft(UNKNOWN_CYCLES), TotalCycles(0), CRD(), IsReady(true), IsZero(false), IndependentFromDef(false) {} const ReadDescriptor &getDescriptor() const { return *RD; } unsigned getSchedClass() const { return RD->SchedClassID; } - unsigned getRegisterID() const { return RegisterID; } + MCPhysReg getRegisterID() const { return RegisterID; } unsigned getRegisterFileID() const { return PRFID; } const CriticalDependency &getCriticalRegDep() const { return CRD; } @@ -272,7 +273,7 @@ public: void setIndependentFromDef() { IndependentFromDef = true; } void cycleEvent(); - void writeStartEvent(unsigned IID, unsigned RegID, unsigned Cycles); + void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles); void setDependentWrites(unsigned Writes) { DependentWrites = Writes; IsReady = !Writes; diff --git a/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp b/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp index 86a888ea8cae..7ea5506f11d6 100644 --- a/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp +++ b/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp @@ -147,7 +147,7 @@ void RegisterFile::freePhysRegs(const RegisterRenamingInfo &Entry, void RegisterFile::addRegisterWrite(WriteRef Write, MutableArrayRef UsedPhysRegs) { WriteState &WS = *Write.getWriteState(); - unsigned RegID = WS.getRegisterID(); + MCPhysReg RegID = WS.getRegisterID(); assert(RegID && "Adding an invalid register definition?"); LLVM_DEBUG({ @@ -194,7 +194,7 @@ void RegisterFile::addRegisterWrite(WriteRef Write, } // Update zero registers. - unsigned ZeroRegisterID = + MCPhysReg ZeroRegisterID = WS.clearsSuperRegisters() ? RegID : WS.getRegisterID(); if (IsWriteZero) { ZeroRegisters.setBit(ZeroRegisterID); @@ -247,7 +247,7 @@ void RegisterFile::removeRegisterWrite( if (WS.isEliminated()) return; - unsigned RegID = WS.getRegisterID(); + MCPhysReg RegID = WS.getRegisterID(); assert(RegID != 0 && "Invalidating an already invalid register?"); assert(WS.getCyclesLeft() != UNKNOWN_CYCLES && @@ -255,7 +255,7 @@ void RegisterFile::removeRegisterWrite( assert(WS.getCyclesLeft() <= 0 && "Invalid cycles left for this write!"); bool ShouldFreePhysRegs = !WS.isWriteZero(); - unsigned RenameAs = RegisterMappings[RegID].second.RenameAs; + MCPhysReg RenameAs = RegisterMappings[RegID].second.RenameAs; if (RenameAs && RenameAs != RegID) { RegID = RenameAs; @@ -355,7 +355,7 @@ bool RegisterFile::tryEliminateMove(WriteState &WS, ReadState &RS) { void RegisterFile::collectWrites(const ReadState &RS, SmallVectorImpl &Writes) const { - unsigned RegID = RS.getRegisterID(); + MCPhysReg RegID = RS.getRegisterID(); assert(RegID && RegID < RegisterMappings.size()); LLVM_DEBUG(dbgs() << "RegisterFile: collecting writes for register " << MRI.getName(RegID) << '\n'); @@ -397,7 +397,7 @@ void RegisterFile::collectWrites(const ReadState &RS, void RegisterFile::addRegisterRead(ReadState &RS, const MCSubtargetInfo &STI) const { - unsigned RegID = RS.getRegisterID(); + MCPhysReg RegID = RS.getRegisterID(); const RegisterRenamingInfo &RRI = RegisterMappings[RegID].second; RS.setPRF(RRI.IndexPlusCost.first); if (RS.isIndependentFromDef()) @@ -424,11 +424,11 @@ void RegisterFile::addRegisterRead(ReadState &RS, } } -unsigned RegisterFile::isAvailable(ArrayRef Regs) const { +unsigned RegisterFile::isAvailable(ArrayRef Regs) const { SmallVector NumPhysRegs(getNumRegisterFiles()); // Find how many new mappings must be created for each register file. - for (const unsigned RegID : Regs) { + for (const MCPhysReg RegID : Regs) { const RegisterRenamingInfo &RRI = RegisterMappings[RegID].second; const IndexPlusCostPairTy &Entry = RRI.IndexPlusCost; if (Entry.first) diff --git a/llvm/lib/MCA/InstrBuilder.cpp b/llvm/lib/MCA/InstrBuilder.cpp index 2a177f6314e8..bd28c733535c 100644 --- a/llvm/lib/MCA/InstrBuilder.cpp +++ b/llvm/lib/MCA/InstrBuilder.cpp @@ -458,9 +458,8 @@ void InstrBuilder::populateReads(InstrDesc &ID, const MCInst &MCI, // FIXME: If an instruction opcode is marked as 'mayLoad', and it has no // "unmodeledSideEffects", then this logic optimistically assumes that any - // extra register operands in the variadic sequence are not register + // extra register operand in the variadic sequence is not a register // definition. - bool AssumeDefsOnly = !MCDesc.mayStore() && MCDesc.mayLoad() && !MCDesc.hasUnmodeledSideEffects(); for (unsigned I = 0, OpIndex = MCDesc.getNumOperands(); @@ -630,8 +629,8 @@ InstrBuilder::createInstruction(const MCInst &MCI) { } // Initialize Reads first. + MCPhysReg RegID = 0; for (const ReadDescriptor &RD : D.Reads) { - int RegID = -1; if (!RD.isImplicitRead()) { // explicit read. const MCOperand &Op = MCI.getOperand(RD.OpIndex); @@ -649,7 +648,6 @@ InstrBuilder::createInstruction(const MCInst &MCI) { continue; // Okay, this is a register operand. Create a ReadState for it. - assert(RegID > 0 && "Invalid register ID found!"); NewIS->getUses().emplace_back(RD, RegID); ReadState &RS = NewIS->getUses().back(); @@ -690,8 +688,8 @@ InstrBuilder::createInstruction(const MCInst &MCI) { // Initialize writes. unsigned WriteIndex = 0; for (const WriteDescriptor &WD : D.Writes) { - unsigned RegID = WD.isImplicitWrite() ? WD.RegisterID - : MCI.getOperand(WD.OpIndex).getReg(); + RegID = WD.isImplicitWrite() ? WD.RegisterID + : MCI.getOperand(WD.OpIndex).getReg(); // Check if this is a optional definition that references NoReg. if (WD.IsOptionalDef && !RegID) { ++WriteIndex; diff --git a/llvm/lib/MCA/Instruction.cpp b/llvm/lib/MCA/Instruction.cpp index 001842bca318..e5f2c4fd1eec 100644 --- a/llvm/lib/MCA/Instruction.cpp +++ b/llvm/lib/MCA/Instruction.cpp @@ -18,7 +18,7 @@ namespace llvm { namespace mca { -void WriteState::writeStartEvent(unsigned IID, unsigned RegID, +void WriteState::writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles) { CRD.IID = IID; CRD.RegID = RegID; @@ -27,7 +27,7 @@ void WriteState::writeStartEvent(unsigned IID, unsigned RegID, DependentWrite = nullptr; } -void ReadState::writeStartEvent(unsigned IID, unsigned RegID, unsigned Cycles) { +void ReadState::writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles) { assert(DependentWrites); assert(CyclesLeft == UNKNOWN_CYCLES); diff --git a/llvm/lib/MCA/Stages/DispatchStage.cpp b/llvm/lib/MCA/Stages/DispatchStage.cpp index 88a7311712e8..3a3d82259160 100644 --- a/llvm/lib/MCA/Stages/DispatchStage.cpp +++ b/llvm/lib/MCA/Stages/DispatchStage.cpp @@ -44,7 +44,7 @@ void DispatchStage::notifyInstructionDispatched(const InstRef &IR, } bool DispatchStage::checkPRF(const InstRef &IR) const { - SmallVector RegDefs; + SmallVector RegDefs; for (const WriteState &RegDef : IR.getInstruction()->getDefs()) RegDefs.emplace_back(RegDef.getRegisterID());