[AArch64] Update v8.5a MTE LDG/STG instructions
The latest MTE specification adds register Xt to the STG instruction family: STG [Xn, #offset] -> STG Xt, [Xn, #offset] The tag written to memory is taken from Xt rather than Xn. Also, the LDG instruction also was changed to read return address from Xt: LDG Xt, [Xn, #offset]. This patch includes those changes and tests. Specification is at: https://developer.arm.com/docs/ddi0596/c Differential Revision: https://reviews.llvm.org/D60188 llvm-svn: 357583
This commit is contained in:
Javed Absar
parent
ee737a84d7
commit
5820db93c9
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@ -4034,8 +4034,9 @@ class MemTagVector<bit Load, string asm_insn, string asm_opnds,
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}
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class MemTagLoad<string asm_insn, string asm_opnds>
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: BaseMemTag<0b01, 0b00, asm_insn, asm_opnds, "", (outs GPR64:$Rt),
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(ins GPR64sp:$Rn, simm9s16:$offset)> {
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: BaseMemTag<0b01, 0b00, asm_insn, asm_opnds, "$Rt = $wback",
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(outs GPR64:$wback),
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(ins GPR64:$Rt, GPR64sp:$Rn, simm9s16:$offset)> {
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bits<5> Rt;
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bits<9> offset;
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@ -4052,29 +4053,28 @@ class BaseMemTagStore<bits<2> opc1, bits<2> opc2, string asm_insn,
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bits<9> offset;
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let Inst{20-12} = offset;
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let Inst{4-0} = 0b11111;
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let Unpredictable{4-0} = 0b11111;
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let Inst{4-0} = Rt;
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let mayStore = 1;
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}
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multiclass MemTagStore<bits<2> opc1, string insn> {
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def Offset :
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BaseMemTagStore<opc1, 0b10, insn, "\t[$Rn, $offset]", "",
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(outs), (ins GPR64sp:$Rn, simm9s16:$offset)>;
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BaseMemTagStore<opc1, 0b10, insn, "\t$Rt, [$Rn, $offset]", "",
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(outs), (ins GPR64sp:$Rt, GPR64sp:$Rn, simm9s16:$offset)>;
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def PreIndex :
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BaseMemTagStore<opc1, 0b11, insn, "\t[$Rn, $offset]!",
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BaseMemTagStore<opc1, 0b11, insn, "\t$Rt, [$Rn, $offset]!",
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"$Rn = $wback,@earlyclobber $wback",
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(outs GPR64sp:$wback),
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(ins GPR64sp:$Rn, simm9s16:$offset)>;
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(ins GPR64sp:$Rt, GPR64sp:$Rn, simm9s16:$offset)>;
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def PostIndex :
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BaseMemTagStore<opc1, 0b01, insn, "\t[$Rn], $offset",
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BaseMemTagStore<opc1, 0b01, insn, "\t$Rt, [$Rn], $offset",
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"$Rn = $wback,@earlyclobber $wback",
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(outs GPR64sp:$wback),
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(ins GPR64sp:$Rn, simm9s16:$offset)>;
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(ins GPR64sp:$Rt, GPR64sp:$Rn, simm9s16:$offset)>;
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def : InstAlias<insn # "\t[$Rn]",
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(!cast<Instruction>(NAME # "Offset") GPR64sp:$Rn, 0)>;
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def : InstAlias<insn # "\t$Rt, [$Rn]",
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(!cast<Instruction>(NAME # "Offset") GPR64sp:$Rt, GPR64sp:$Rn, 0)>;
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}
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//---
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@ -184,22 +184,29 @@ gmi x0, x1, #1
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// CHECK-NEXT: gmi x0, #1, x2
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: gmi x0, x1, #1
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stg
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stg x0
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stg [xzr]
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stg [x0, #-4112]
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stg [x0, #4096]
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stg [x0, #8]
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stg [x0, x1]
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stg [w0]
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stg w0
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stg sp
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stg #1
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stg x0, [x0, #-4112]
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stg x0, [x0, #4096]
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stg x0, [x0, #8]
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stg x0, [x0, x1]
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stg x0, [w0]
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stg x0, [xzr]
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stg x0, [#1]
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// CHECK: too few operands for instruction
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// CHECK-NEXT: stg
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// CHECK: invalid operand for instruction
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// CHECK: too few operands for instruction
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// CHECK-NEXT: stg x0
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: [xzr]
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// CHECK-NEXT: stg w0
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// CHECK: too few operands for instruction
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// CHECK-NEXT: stg sp
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stg #1
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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// CHECK-NEXT: #-4112
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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@ -207,25 +214,37 @@ stg [w0]
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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// CHECK-NEXT: #8
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stg [x0, x1]
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// CHECK-NEXT: stg x0, [x0, x1]
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stg [w0]
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// CHECK-NEXT: stg x0, [w0]
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stg x0, [xzr]
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stg x0, [#1]
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stzg
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stzg x0
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stzg [xzr]
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stzg [x0, #-4112]
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stzg [x0, #4096]
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stzg [x0, #8]
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stzg [x0, x1]
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stzg [w0]
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stzg w0
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stzg sp
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stzg #1
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stzg x0, [x0, #-4112]
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stzg x0, [x0, #4096]
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stzg x0, [x0, #8]
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stzg x0, [x0, x1]
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stzg x0, [w0]
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stzg x0, [xzr]
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stzg x0, [#1]
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// CHECK: too few operands for instruction
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// CHECK-NEXT: stzg
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// CHECK: invalid operand for instruction
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// CHECK: too few operands for instruction
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// CHECK-NEXT: stzg x0
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: [xzr]
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// CHECK-NEXT: stzg w0
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// CHECK: too few operands for instruction
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// CHECK-NEXT: stzg sp
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stzg #1
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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// CHECK-NEXT: #-4112
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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@ -233,15 +252,21 @@ stzg [w0]
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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// CHECK-NEXT: #8
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stzg [x0, x1]
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// CHECK-NEXT: stzg x0, [x0, x1]
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stzg [w0]
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// CHECK-NEXT: stzg x0, [w0]
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stzg x0, [xzr]
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stzg x0, [#1]
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stg [x0, #-4112]!
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stg [x0, #4096]!
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stg [x0, #8]!
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stg [x0, x1]!
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stg [w0, #255]!
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stg x0, [x0, #-4112]!
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stg x0, [x0, #4096]!
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stg x0, [x0, #8]!
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stg x0, [x0, x1]!
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stg x0, [w0]!
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stg x0, [xzr]!
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stg x0, [#1]!
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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// CHECK-NEXT: #-4112
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@ -250,15 +275,21 @@ stg [w0, #255]!
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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// CHECK-NEXT: #8
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stg [x0, x1]!
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// CHECK-NEXT: stg x0, [x0, x1]!
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stg [w0, #255]!
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// CHECK-NEXT: stg x0, [w0]!
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stg x0, [xzr]!
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stg x0, [#1]!
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stzg [x0, #-4112]!
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stzg [x0, #4096]!
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stzg [x0, #8]!
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stzg [x0, x1]!
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stzg [w0, #255]!
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stzg x0, [x0, #-4112]!
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stzg x0, [x0, #4096]!
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stzg x0, [x0, #8]!
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stzg x0, [x0, x1]!
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stzg x0, [w0]!
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stzg x0, [xzr]!
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stzg x0, [#1]!
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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// CHECK-NEXT: #-4112
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@ -267,15 +298,21 @@ stzg [w0, #255]!
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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// CHECK-NEXT: #8
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stzg [x0, x1]!
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// CHECK-NEXT: stzg x0, [x0, x1]!
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stzg [w0, #255]!
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// CHECK-NEXT: stzg x0, [w0]!
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stzg x0, [xzr]!
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stzg x0, [#1]!
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stg [x0], #-4112
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stg [x0], #4096
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stg [x0], #8
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stg [x0], x1
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stg [w0], #255
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stg x0, [x0], #-4112
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stg x0, [x0], #4096
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stg x0, [x0], #8
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stg x0, [x0], x1
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stg x0, [w0], #255
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stg x0, [xzr], #255
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stg x0, [#1], #255
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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// CHECK-NEXT: #-4112
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@ -284,15 +321,21 @@ stg [w0], #255
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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// CHECK-NEXT: #8
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stg [x0], x1
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// CHECK-NEXT: stg x0, [x0], x1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stg [w0], #255
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// CHECK-NEXT: stg x0, [w0], #255
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stg x0, [xzr], #255
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stg x0, [#1], #255
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stzg [x0], #-4112
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stzg [x0], #4096
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stzg [x0], #8
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stzg [x0], x1
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stzg [w0], #255
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stzg x0, [x0], #-4112
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stzg x0, [x0], #4096
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stzg x0, [x0], #8
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stzg x0, [x0], x1
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stzg x0, [w0], #255
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stzg x0, [xzr], #255
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stzg x0, [#1], #255
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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// CHECK-NEXT: #-4112
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@ -301,25 +344,37 @@ stzg [w0], #255
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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// CHECK-NEXT: #8
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stzg [x0], x1
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// CHECK-NEXT: stzg x0, [x0], x1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stzg [w0], #255
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// CHECK-NEXT: stzg x0, [w0], #255
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stzg x0, [xzr], #255
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stzg x0, [#1], #255
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st2g
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st2g x0
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st2g [xzr]
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st2g [x0, #-4112]
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st2g [x0, #4096]
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st2g [x0, #8]
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st2g [x0, x1]
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st2g [w0]
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st2g w0
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st2g sp
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st2g #1
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st2g x0, [x0, #-4112]
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st2g x0, [x0, #4096]
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st2g x0, [x0, #8]
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st2g x0, [x0, x1]
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st2g x0, [w0]
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st2g x0, [xzr]
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st2g x0, [#1]
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// CHECK: too few operands for instruction
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// CHECK-NEXT: st2g
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// CHECK: invalid operand for instruction
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// CHECK: too few operands for instruction
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// CHECK-NEXT: st2g x0
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: [xzr]
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// CHECK-NEXT: st2g w0
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// CHECK: too few operands for instruction
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// CHECK-NEXT: st2g sp
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: st2g #1
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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// CHECK-NEXT: #-4112
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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@ -327,22 +382,37 @@ st2g [w0]
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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// CHECK-NEXT: #8
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: st2g [x0, x1]
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// CHECK-NEXT: st2g x0, [x0, x1]
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: st2g [w0]
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// CHECK-NEXT: st2g x0, [w0]
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: st2g x0, [xzr]
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: st2g x0, [#1]
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stz2g
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stz2g [xzr]
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stz2g [x0, #-4112]
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stz2g [x0, #4096]
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stz2g [x0, #8]
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stz2g [x0, x1]
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stz2g [w0]
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stz2g x0
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stz2g w0
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stz2g sp
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stz2g #1
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stz2g x0, [x0, #-4112]
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stz2g x0, [x0, #4096]
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stz2g x0, [x0, #8]
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stz2g x0, [x0, x1]
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stz2g x0, [w0]
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stz2g x0, [xzr]
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stz2g x0, [#1]
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// CHECK: too few operands for instruction
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// CHECK-NEXT: stz2g
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// CHECK: too few operands for instruction
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// CHECK-NEXT: stz2g x0
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: [xzr]
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// CHECK-NEXT: stz2g w0
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// CHECK: too few operands for instruction
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// CHECK-NEXT: stz2g sp
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stz2g #1
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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// CHECK-NEXT: #-4112
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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@ -350,15 +420,21 @@ stz2g [w0]
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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// CHECK-NEXT: #8
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stz2g [x0, x1]
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// CHECK-NEXT: stz2g x0, [x0, x1]
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stz2g [w0]
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// CHECK-NEXT: stz2g x0, [w0]
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stz2g x0, [xzr]
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: stz2g x0, [#1]
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st2g [x0, #-4112]!
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st2g [x0, #4096]!
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st2g [x0, #8]!
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st2g [x0, x1]!
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st2g [w0, #255]!
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st2g x0, [x0, #-4112]!
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st2g x0, [x0, #4096]!
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st2g x0, [x0, #8]!
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st2g x0, [x0, x1]!
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st2g x0, [w0, #256]!
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st2g x0, [xzr, #256]!
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st2g x0, [#1, #256]!
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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// CHECK-NEXT: #-4112
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@ -367,15 +443,21 @@ st2g [w0, #255]!
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// CHECK: index must be a multiple of 16 in range [-4096, 4080]
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// CHECK-NEXT: #8
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: st2g [x0, x1]!
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// CHECK-NEXT: st2g x0, [x0, x1]!
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: st2g [w0, #255]!
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// CHECK-NEXT: st2g x0, [w0, #256]!
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: st2g x0, [xzr, #256]!
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: st2g x0, [#1, #256]!
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stz2g [x0, #-4112]!
|
||||
stz2g [x0, #4096]!
|
||||
stz2g [x0, #8]!
|
||||
stz2g [x0, x1]!
|
||||
stz2g [w0, #255]!
|
||||
stz2g x0, [x0, #-4112]!
|
||||
stz2g x0, [x0, #4096]!
|
||||
stz2g x0, [x0, #8]!
|
||||
stz2g x0, [x0, x1]!
|
||||
stz2g x0, [w0, #255]!
|
||||
stz2g x0, [xzr, #255]!
|
||||
stz2g x0, [#1, #255]!
|
||||
|
||||
// CHECK: index must be a multiple of 16 in range [-4096, 4080]
|
||||
// CHECK-NEXT: #-4112
|
||||
|
|
@ -384,15 +466,21 @@ stz2g [w0, #255]!
|
|||
// CHECK: index must be a multiple of 16 in range [-4096, 4080]
|
||||
// CHECK-NEXT: #8
|
||||
// CHECK: invalid operand for instruction
|
||||
// CHECK-NEXT: stz2g [x0, x1]!
|
||||
// CHECK-NEXT: stz2g x0, [x0, x1]!
|
||||
// CHECK: invalid operand for instruction
|
||||
// CHECK-NEXT: stz2g [w0, #255]!
|
||||
// CHECK-NEXT: stz2g x0, [w0, #255]!
|
||||
// CHECK: invalid operand for instruction
|
||||
// CHECK-NEXT: stz2g x0, [xzr, #255]!
|
||||
// CHECK: invalid operand for instruction
|
||||
// CHECK-NEXT: stz2g x0, [#1, #255]!
|
||||
|
||||
st2g [x0], #-4112
|
||||
st2g [x0], #4096
|
||||
st2g [x0], #8
|
||||
st2g [x0], x1
|
||||
st2g [#1], #255
|
||||
st2g x0, [x0], #-4112
|
||||
st2g x0, [x0], #4096
|
||||
st2g x0, [x0], #8
|
||||
st2g x0, [x0], x1
|
||||
st2g x0, [w0], #255
|
||||
st2g x0, [xzr], #255
|
||||
st2g x0, [#1], #255
|
||||
|
||||
// CHECK: index must be a multiple of 16 in range [-4096, 4080]
|
||||
// CHECK-NEXT: #-4112
|
||||
|
|
@ -401,15 +489,21 @@ st2g [#1], #255
|
|||
// CHECK: index must be a multiple of 16 in range [-4096, 4080]
|
||||
// CHECK-NEXT: #8
|
||||
// CHECK: invalid operand for instruction
|
||||
// CHECK-NEXT: st2g [x0], x1
|
||||
// CHECK-NEXT: st2g x0, [x0], x1
|
||||
// CHECK: invalid operand for instruction
|
||||
// CHECK-NEXT: st2g [#1], #255
|
||||
// CHECK-NEXT: st2g x0, [w0], #255
|
||||
// CHECK: invalid operand for instruction
|
||||
// CHECK-NEXT: st2g x0, [xzr], #255
|
||||
// CHECK: invalid operand for instruction
|
||||
// CHECK-NEXT: st2g x0, [#1], #255
|
||||
|
||||
stz2g [x0], #-4112
|
||||
stz2g [x0], #4096
|
||||
stz2g [x0], #8
|
||||
stz2g [x0], x1
|
||||
stz2g [#0], x1
|
||||
stz2g x0, [x0], #-4112
|
||||
stz2g x0, [x0], #4096
|
||||
stz2g x0, [x0], #8
|
||||
stz2g x0, [x0], x1
|
||||
stz2g x0, [w0], #255
|
||||
stz2g x0, [xzr], #255
|
||||
stz2g x0, [#1], #255
|
||||
|
||||
// CHECK: index must be a multiple of 16 in range [-4096, 4080]
|
||||
// CHECK-NEXT: #-4112
|
||||
|
|
@ -418,9 +512,13 @@ stz2g [#0], x1
|
|||
// CHECK: index must be a multiple of 16 in range [-4096, 4080]
|
||||
// CHECK-NEXT: #8
|
||||
// CHECK: invalid operand for instruction
|
||||
// CHECK-NEXT: stz2g [x0], x1
|
||||
// CHECK-NEXT: stz2g x0, [x0], x1
|
||||
// CHECK: invalid operand for instruction
|
||||
// CHECK-NEXT: stz2g [#0], x1
|
||||
// CHECK-NEXT: stz2g x0, [w0], #255
|
||||
// CHECK: invalid operand for instruction
|
||||
// CHECK-NEXT: stz2g x0, [xzr], #255
|
||||
// CHECK: invalid operand for instruction
|
||||
// CHECK-NEXT: stz2g x0, [#1], #255
|
||||
|
||||
stgp sp, x1, [x2, #16]
|
||||
stgp x0, sp, [x2, #16]
|
||||
|
|
@ -678,6 +776,7 @@ msr tfsr_el2, #4
|
|||
msr tfsr_el3, #5
|
||||
msr tfsr_el12, #6
|
||||
msr tfsre0_el1, #7
|
||||
// Is read only
|
||||
msr gmid_el1, #7
|
||||
|
||||
// CHECK: invalid operand for instruction
|
||||
|
|
|
|||
|
|
@ -90,15 +90,61 @@ gmi x30, x0, xzr
|
|||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: gmi x30, x0, xzr
|
||||
|
||||
stg [x1]
|
||||
stg [x1, #-4096]
|
||||
stg [x2, #4080]
|
||||
stg [sp, #16]
|
||||
stg x0, [x1]
|
||||
stg x1, [x1, #-4096]
|
||||
stg x2, [x2, #4080]
|
||||
stg x3, [sp, #16]
|
||||
stg sp, [sp, #16]
|
||||
|
||||
// CHECK: stg [x1] // encoding: [0x3f,0x08,0x20,0xd9]
|
||||
// CHECK: stg [x1, #-4096] // encoding: [0x3f,0x08,0x30,0xd9]
|
||||
// CHECK: stg [x2, #4080] // encoding: [0x5f,0xf8,0x2f,0xd9]
|
||||
// CHECK: stg [sp, #16] // encoding: [0xff,0x1b,0x20,0xd9]
|
||||
// CHECK: stg x0, [x1] // encoding: [0x20,0x08,0x20,0xd9]
|
||||
// CHECK: stg x1, [x1, #-4096] // encoding: [0x21,0x08,0x30,0xd9]
|
||||
// CHECK: stg x2, [x2, #4080] // encoding: [0x42,0xf8,0x2f,0xd9]
|
||||
// CHECK: stg x3, [sp, #16] // encoding: [0xe3,0x1b,0x20,0xd9]
|
||||
// CHECK: stg sp, [sp, #16] // encoding: [0xff,0x1b,0x20,0xd9]
|
||||
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stg
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stg
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stg
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stg
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stg
|
||||
|
||||
stzg x0, [x1]
|
||||
stzg x1, [x1, #-4096]
|
||||
stzg x2, [x2, #4080]
|
||||
stzg x3, [sp, #16]
|
||||
stzg sp, [sp, #16]
|
||||
|
||||
// CHECK: stzg x0, [x1] // encoding: [0x20,0x08,0x60,0xd9]
|
||||
// CHECK: stzg x1, [x1, #-4096] // encoding: [0x21,0x08,0x70,0xd9]
|
||||
// CHECK: stzg x2, [x2, #4080] // encoding: [0x42,0xf8,0x6f,0xd9]
|
||||
// CHECK: stzg x3, [sp, #16] // encoding: [0xe3,0x1b,0x60,0xd9]
|
||||
// CHECK: stzg sp, [sp, #16] // encoding: [0xff,0x1b,0x60,0xd9]
|
||||
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stzg
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stzg
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stzg
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stzg
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stzg
|
||||
|
||||
stg x0, [x1, #-4096]!
|
||||
stg x1, [x2, #4080]!
|
||||
stg x2, [sp, #16]!
|
||||
stg sp, [sp, #16]!
|
||||
|
||||
// CHECK: stg x0, [x1, #-4096]! // encoding: [0x20,0x0c,0x30,0xd9]
|
||||
// CHECK: stg x1, [x2, #4080]! // encoding: [0x41,0xfc,0x2f,0xd9]
|
||||
// CHECK: stg x2, [sp, #16]! // encoding: [0xe2,0x1f,0x20,0xd9]
|
||||
// CHECK: stg sp, [sp, #16]! // encoding: [0xff,0x1f,0x20,0xd9]
|
||||
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stg
|
||||
|
|
@ -109,15 +155,15 @@ stg [sp, #16]
|
|||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stg
|
||||
|
||||
stzg [x1]
|
||||
stzg [x1, #-4096]
|
||||
stzg [x2, #4080]
|
||||
stzg [sp, #16]
|
||||
stzg x0, [x1, #-4096]!
|
||||
stzg x1, [x2, #4080]!
|
||||
stzg x2, [sp, #16]!
|
||||
stzg sp, [sp, #16]!
|
||||
|
||||
// CHECK: stzg [x1] // encoding: [0x3f,0x08,0x60,0xd9]
|
||||
// CHECK: stzg [x1, #-4096] // encoding: [0x3f,0x08,0x70,0xd9]
|
||||
// CHECK: stzg [x2, #4080] // encoding: [0x5f,0xf8,0x6f,0xd9]
|
||||
// CHECK: stzg [sp, #16] // encoding: [0xff,0x1b,0x60,0xd9]
|
||||
// CHECK: stzg x0, [x1, #-4096]! // encoding: [0x20,0x0c,0x70,0xd9]
|
||||
// CHECK: stzg x1, [x2, #4080]! // encoding: [0x41,0xfc,0x6f,0xd9]
|
||||
// CHECK: stzg x2, [sp, #16]! // encoding: [0xe2,0x1f,0x60,0xd9]
|
||||
// CHECK: stzg sp, [sp, #16]! // encoding: [0xff,0x1f,0x60,0xd9]
|
||||
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stzg
|
||||
|
|
@ -128,44 +174,18 @@ stzg [sp, #16]
|
|||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stzg
|
||||
|
||||
stg [x1, #-4096]!
|
||||
stg [x2, #4080]!
|
||||
stg [sp, #16]!
|
||||
stg x0, [x1], #-4096
|
||||
stg x1, [x2], #4080
|
||||
stg x2, [sp], #16
|
||||
stg sp, [sp], #16
|
||||
|
||||
// CHECK: stg [x1, #-4096]! // encoding: [0x3f,0x0c,0x30,0xd9]
|
||||
// CHECK: stg [x2, #4080]! // encoding: [0x5f,0xfc,0x2f,0xd9]
|
||||
// CHECK: stg [sp, #16]! // encoding: [0xff,0x1f,0x20,0xd9]
|
||||
// CHECK: stg x0, [x1], #-4096 // encoding: [0x20,0x04,0x30,0xd9]
|
||||
// CHECK: stg x1, [x2], #4080 // encoding: [0x41,0xf4,0x2f,0xd9]
|
||||
// CHECK: stg x2, [sp], #16 // encoding: [0xe2,0x17,0x20,0xd9]
|
||||
// CHECK: stg sp, [sp], #16 // encoding: [0xff,0x17,0x20,0xd9]
|
||||
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stg
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stg
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stg
|
||||
|
||||
stzg [x1, #-4096]!
|
||||
stzg [x2, #4080]!
|
||||
stzg [sp, #16]!
|
||||
|
||||
// CHECK: stzg [x1, #-4096]! // encoding: [0x3f,0x0c,0x70,0xd9]
|
||||
// CHECK: stzg [x2, #4080]! // encoding: [0x5f,0xfc,0x6f,0xd9]
|
||||
// CHECK: stzg [sp, #16]! // encoding: [0xff,0x1f,0x60,0xd9]
|
||||
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stzg
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stzg
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stzg
|
||||
|
||||
stg [x1], #-4096
|
||||
stg [x2], #4080
|
||||
stg [sp], #16
|
||||
|
||||
// CHECK: stg [x1], #-4096 // encoding: [0x3f,0x04,0x30,0xd9]
|
||||
// CHECK: stg [x2], #4080 // encoding: [0x5f,0xf4,0x2f,0xd9]
|
||||
// CHECK: stg [sp], #16 // encoding: [0xff,0x17,0x20,0xd9]
|
||||
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stg
|
||||
// NOMTE: instruction requires: mte
|
||||
|
|
@ -173,13 +193,15 @@ stg [sp], #16
|
|||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stg
|
||||
|
||||
stzg [x1], #-4096
|
||||
stzg [x2], #4080
|
||||
stzg [sp], #16
|
||||
stzg x0, [x1], #-4096
|
||||
stzg x1, [x2], #4080
|
||||
stzg x2, [sp], #16
|
||||
stzg sp, [sp], #16
|
||||
|
||||
// CHECK: stzg [x1], #-4096 // encoding: [0x3f,0x04,0x70,0xd9]
|
||||
// CHECK: stzg [x2], #4080 // encoding: [0x5f,0xf4,0x6f,0xd9]
|
||||
// CHECK: stzg [sp], #16 // encoding: [0xff,0x17,0x60,0xd9]
|
||||
// CHECK: stzg x0, [x1], #-4096 // encoding: [0x20,0x04,0x70,0xd9]
|
||||
// CHECK: stzg x1, [x2], #4080 // encoding: [0x41,0xf4,0x6f,0xd9]
|
||||
// CHECK: stzg x2, [sp], #16 // encoding: [0xe2,0x17,0x60,0xd9]
|
||||
// CHECK: stzg sp, [sp], #16 // encoding: [0xff,0x17,0x60,0xd9]
|
||||
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stzg
|
||||
|
|
@ -187,16 +209,64 @@ stzg [sp], #16
|
|||
// NOMTE-NEXT: stzg
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stzg
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stzg
|
||||
|
||||
st2g [x1]
|
||||
st2g [x1, #-4096]
|
||||
st2g [x2, #4080]
|
||||
st2g [sp, #16]
|
||||
st2g x0, [x1]
|
||||
st2g x1, [x1, #-4096]
|
||||
st2g x2, [x2, #4080]
|
||||
st2g x3, [sp, #16]
|
||||
st2g sp, [sp, #16]
|
||||
|
||||
// CHECK: st2g [x1] // encoding: [0x3f,0x08,0xa0,0xd9]
|
||||
// CHECK: st2g [x1, #-4096] // encoding: [0x3f,0x08,0xb0,0xd9]
|
||||
// CHECK: st2g [x2, #4080] // encoding: [0x5f,0xf8,0xaf,0xd9]
|
||||
// CHECK: st2g [sp, #16] // encoding: [0xff,0x1b,0xa0,0xd9]
|
||||
// CHECK: st2g x0, [x1] // encoding: [0x20,0x08,0xa0,0xd9]
|
||||
// CHECK: st2g x1, [x1, #-4096] // encoding: [0x21,0x08,0xb0,0xd9]
|
||||
// CHECK: st2g x2, [x2, #4080] // encoding: [0x42,0xf8,0xaf,0xd9]
|
||||
// CHECK: st2g x3, [sp, #16] // encoding: [0xe3,0x1b,0xa0,0xd9]
|
||||
// CHECK: st2g sp, [sp, #16] // encoding: [0xff,0x1b,0xa0,0xd9]
|
||||
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: st2g
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: st2g
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: st2g
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: st2g
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: st2g
|
||||
|
||||
stz2g x0, [x1]
|
||||
stz2g x1, [x1, #-4096]
|
||||
stz2g x2, [x2, #4080]
|
||||
stz2g x3, [sp, #16]
|
||||
stz2g sp, [sp, #16]
|
||||
|
||||
// CHECK: stz2g x0, [x1] // encoding: [0x20,0x08,0xe0,0xd9]
|
||||
// CHECK: stz2g x1, [x1, #-4096] // encoding: [0x21,0x08,0xf0,0xd9]
|
||||
// CHECK: stz2g x2, [x2, #4080] // encoding: [0x42,0xf8,0xef,0xd9]
|
||||
// CHECK: stz2g x3, [sp, #16] // encoding: [0xe3,0x1b,0xe0,0xd9]
|
||||
// CHECK: stz2g sp, [sp, #16] // encoding: [0xff,0x1b,0xe0,0xd9]
|
||||
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stz2g
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stz2g
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stz2g
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stz2g
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stz2g
|
||||
|
||||
st2g x0, [x1, #-4096]!
|
||||
st2g x1, [x2, #4080]!
|
||||
st2g x2, [sp, #16]!
|
||||
st2g sp, [sp, #16]!
|
||||
|
||||
// CHECK: st2g x0, [x1, #-4096]! // encoding: [0x20,0x0c,0xb0,0xd9]
|
||||
// CHECK: st2g x1, [x2, #4080]! // encoding: [0x41,0xfc,0xaf,0xd9]
|
||||
// CHECK: st2g x2, [sp, #16]! // encoding: [0xe2,0x1f,0xa0,0xd9]
|
||||
// CHECK: st2g sp, [sp, #16]! // encoding: [0xff,0x1f,0xa0,0xd9]
|
||||
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: st2g
|
||||
|
|
@ -207,15 +277,15 @@ st2g [sp, #16]
|
|||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: st2g
|
||||
|
||||
stz2g [x1]
|
||||
stz2g [x1, #-4096]
|
||||
stz2g [x2, #4080]
|
||||
stz2g [sp, #16]
|
||||
stz2g x0, [x1, #-4096]!
|
||||
stz2g x1, [x2, #4080]!
|
||||
stz2g x2, [sp, #16]!
|
||||
stz2g sp, [sp, #16]!
|
||||
|
||||
// CHECK: stz2g [x1] // encoding: [0x3f,0x08,0xe0,0xd9]
|
||||
// CHECK: stz2g [x1, #-4096] // encoding: [0x3f,0x08,0xf0,0xd9]
|
||||
// CHECK: stz2g [x2, #4080] // encoding: [0x5f,0xf8,0xef,0xd9]
|
||||
// CHECK: stz2g [sp, #16] // encoding: [0xff,0x1b,0xe0,0xd9]
|
||||
// CHECK: stz2g x0, [x1, #-4096]! // encoding: [0x20,0x0c,0xf0,0xd9]
|
||||
// CHECK: stz2g x1, [x2, #4080]! // encoding: [0x41,0xfc,0xef,0xd9]
|
||||
// CHECK: stz2g x2, [sp, #16]! // encoding: [0xe2,0x1f,0xe0,0xd9]
|
||||
// CHECK: stz2g sp, [sp, #16]! // encoding: [0xff,0x1f,0xe0,0xd9]
|
||||
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stz2g
|
||||
|
|
@ -226,13 +296,15 @@ stz2g [sp, #16]
|
|||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stz2g
|
||||
|
||||
st2g [x1, #-4096]!
|
||||
st2g [x2, #4080]!
|
||||
st2g [sp, #16]!
|
||||
st2g x0, [x1], #-4096
|
||||
st2g x1, [x2], #4080
|
||||
st2g x2, [sp], #16
|
||||
st2g sp, [sp], #16
|
||||
|
||||
// CHECK: st2g [x1, #-4096]! // encoding: [0x3f,0x0c,0xb0,0xd9]
|
||||
// CHECK: st2g [x2, #4080]! // encoding: [0x5f,0xfc,0xaf,0xd9]
|
||||
// CHECK: st2g [sp, #16]! // encoding: [0xff,0x1f,0xa0,0xd9]
|
||||
// CHECK: st2g x0, [x1], #-4096 // encoding: [0x20,0x04,0xb0,0xd9]
|
||||
// CHECK: st2g x1, [x2], #4080 // encoding: [0x41,0xf4,0xaf,0xd9]
|
||||
// CHECK: st2g x2, [sp], #16 // encoding: [0xe2,0x17,0xa0,0xd9]
|
||||
// CHECK: st2g sp, [sp], #16 // encoding: [0xff,0x17,0xa0,0xd9]
|
||||
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: st2g
|
||||
|
|
@ -240,45 +312,21 @@ st2g [sp, #16]!
|
|||
// NOMTE-NEXT: st2g
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: st2g
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: st2g
|
||||
|
||||
stz2g [x1, #-4096]!
|
||||
stz2g [x2, #4080]!
|
||||
stz2g [sp, #16]!
|
||||
stz2g x0, [x1], #-4096
|
||||
stz2g x1, [x2], #4080
|
||||
stz2g x2, [sp], #16
|
||||
stz2g sp, [sp], #16
|
||||
|
||||
// CHECK: stz2g [x1, #-4096]! // encoding: [0x3f,0x0c,0xf0,0xd9]
|
||||
// CHECK: stz2g [x2, #4080]! // encoding: [0x5f,0xfc,0xef,0xd9]
|
||||
// CHECK: stz2g [sp, #16]! // encoding: [0xff,0x1f,0xe0,0xd9]
|
||||
// CHECK: stz2g x0, [x1], #-4096 // encoding: [0x20,0x04,0xf0,0xd9]
|
||||
// CHECK: stz2g x1, [x2], #4080 // encoding: [0x41,0xf4,0xef,0xd9]
|
||||
// CHECK: stz2g x2, [sp], #16 // encoding: [0xe2,0x17,0xe0,0xd9]
|
||||
// CHECK: stz2g sp, [sp], #16 // encoding: [0xff,0x17,0xe0,0xd9]
|
||||
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stz2g
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stz2g
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stz2g
|
||||
|
||||
st2g [x1], #-4096
|
||||
st2g [x2], #4080
|
||||
st2g [sp], #16
|
||||
|
||||
// CHECK: st2g [x1], #-4096 // encoding: [0x3f,0x04,0xb0,0xd9]
|
||||
// CHECK: st2g [x2], #4080 // encoding: [0x5f,0xf4,0xaf,0xd9]
|
||||
// CHECK: st2g [sp], #16 // encoding: [0xff,0x17,0xa0,0xd9]
|
||||
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: st2g
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: st2g
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: st2g
|
||||
|
||||
stz2g [x1], #-4096
|
||||
stz2g [x2], #4080
|
||||
stz2g [sp], #16
|
||||
|
||||
// CHECK: stz2g [x1], #-4096 // encoding: [0x3f,0x04,0xf0,0xd9]
|
||||
// CHECK: stz2g [x2], #4080 // encoding: [0x5f,0xf4,0xef,0xd9]
|
||||
// CHECK: stz2g [sp], #16 // encoding: [0xff,0x17,0xe0,0xd9]
|
||||
|
||||
// NOMTE: instruction requires: mte
|
||||
// NOMTE-NEXT: stz2g
|
||||
// NOMTE: instruction requires: mte
|
||||
|
|
|
|||
|
|
@ -117,199 +117,248 @@
|
|||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xff,0x03,0xdf,0xba]
|
||||
|
||||
[0x3f,0x08,0x30,0xd9]
|
||||
[0x5f,0xf8,0x2f,0xd9]
|
||||
[0xff,0x1b,0x20,0xd9]
|
||||
[0x20,0x08,0x30,0xd9]
|
||||
[0x41,0xf8,0x2f,0xd9]
|
||||
[0xe2,0x1b,0x20,0xd9]
|
||||
[0x23,0x08,0x20,0xd9]
|
||||
[0x3f,0x08,0x20,0xd9]
|
||||
|
||||
# CHECK: stg [x1, #-4096]
|
||||
# CHECK: stg [x2, #4080]
|
||||
# CHECK: stg [sp, #16]
|
||||
# CHECK: stg [x1]
|
||||
# CHECK: stg x0, [x1, #-4096]
|
||||
# CHECK: stg x1, [x2, #4080]
|
||||
# CHECK: stg x2, [sp, #16]
|
||||
# CHECK: stg x3, [x1]
|
||||
# CHECK: stg sp, [x1]
|
||||
|
||||
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x3f,0x08,0x30,0xd9]
|
||||
# NOMTE-NEXT: [0x20,0x08,0x30,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x5f,0xf8,0x2f,0xd9]
|
||||
# NOMTE-NEXT: [0x41,0xf8,0x2f,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xff,0x1b,0x20,0xd9]
|
||||
# NOMTE-NEXT: [0xe2,0x1b,0x20,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x23,0x08,0x20,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x3f,0x08,0x20,0xd9]
|
||||
|
||||
[0x3f,0x08,0x70,0xd9]
|
||||
[0x5f,0xf8,0x6f,0xd9]
|
||||
[0xff,0x1b,0x60,0xd9]
|
||||
[0x20,0x08,0x70,0xd9]
|
||||
[0x41,0xf8,0x6f,0xd9]
|
||||
[0xe2,0x1b,0x60,0xd9]
|
||||
[0x23,0x08,0x60,0xd9]
|
||||
[0x3f,0x08,0x60,0xd9]
|
||||
|
||||
# CHECK: stzg [x1, #-4096]
|
||||
# CHECK: stzg [x2, #4080]
|
||||
# CHECK: stzg [sp, #16]
|
||||
# CHECK: stzg [x1]
|
||||
# CHECK: stzg x0, [x1, #-4096]
|
||||
# CHECK: stzg x1, [x2, #4080]
|
||||
# CHECK: stzg x2, [sp, #16]
|
||||
# CHECK: stzg x3, [x1]
|
||||
# CHECK: stzg sp, [x1]
|
||||
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x3f,0x08,0x70,0xd9]
|
||||
# NOMTE-NEXT: [0x20,0x08,0x70,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x5f,0xf8,0x6f,0xd9]
|
||||
# NOMTE-NEXT: [0x41,0xf8,0x6f,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xff,0x1b,0x60,0xd9]
|
||||
# NOMTE-NEXT: [0xe2,0x1b,0x60,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x23,0x08,0x60,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x3f,0x08,0x60,0xd9]
|
||||
|
||||
[0x3f,0x0c,0x30,0xd9]
|
||||
[0x5f,0xfc,0x2f,0xd9]
|
||||
[0x20,0x0c,0x30,0xd9]
|
||||
[0x41,0xfc,0x2f,0xd9]
|
||||
[0xe2,0x1f,0x20,0xd9]
|
||||
[0xff,0x1f,0x20,0xd9]
|
||||
|
||||
# CHECK: stg [x1, #-4096]!
|
||||
# CHECK: stg [x2, #4080]!
|
||||
# CHECK: stg [sp, #16]!
|
||||
# CHECK: stg x0, [x1, #-4096]!
|
||||
# CHECK: stg x1, [x2, #4080]!
|
||||
# CHECK: stg x2, [sp, #16]!
|
||||
# CHECK: stg sp, [sp, #16]!
|
||||
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x3f,0x0c,0x30,0xd9]
|
||||
# NOMTE-NEXT: [0x20,0x0c,0x30,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x5f,0xfc,0x2f,0xd9]
|
||||
# NOMTE-NEXT: [0x41,0xfc,0x2f,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xe2,0x1f,0x20,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xff,0x1f,0x20,0xd9]
|
||||
|
||||
[0x3f,0x0c,0x70,0xd9]
|
||||
[0x5f,0xfc,0x6f,0xd9]
|
||||
[0x20,0x0c,0x70,0xd9]
|
||||
[0x41,0xfc,0x6f,0xd9]
|
||||
[0xe2,0x1f,0x60,0xd9]
|
||||
[0xff,0x1f,0x60,0xd9]
|
||||
|
||||
# CHECK: stzg [x1, #-4096]!
|
||||
# CHECK: stzg [x2, #4080]!
|
||||
# CHECK: stzg [sp, #16]!
|
||||
# CHECK: stzg x0, [x1, #-4096]!
|
||||
# CHECK: stzg x1, [x2, #4080]!
|
||||
# CHECK: stzg x2, [sp, #16]!
|
||||
# CHECK: stzg sp, [sp, #16]!
|
||||
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x3f,0x0c,0x70,0xd9]
|
||||
# NOMTE-NEXT: [0x20,0x0c,0x70,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x5f,0xfc,0x6f,0xd9]
|
||||
# NOMTE-NEXT: [0x41,0xfc,0x6f,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xe2,0x1f,0x60,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xff,0x1f,0x60,0xd9]
|
||||
|
||||
[0x3f,0x04,0x30,0xd9]
|
||||
[0x5f,0xf4,0x2f,0xd9]
|
||||
[0x20,0x04,0x30,0xd9]
|
||||
[0x41,0xf4,0x2f,0xd9]
|
||||
[0xe2,0x17,0x20,0xd9]
|
||||
[0xff,0x17,0x20,0xd9]
|
||||
|
||||
# CHECK: stg [x1], #-4096
|
||||
# CHECK: stg [x2], #4080
|
||||
# CHECK: stg [sp], #16
|
||||
# CHECK: stg x0, [x1], #-4096
|
||||
# CHECK: stg x1, [x2], #4080
|
||||
# CHECK: stg x2, [sp], #16
|
||||
# CHECK: stg sp, [sp], #16
|
||||
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x3f,0x04,0x30,0xd9]
|
||||
# NOMTE-NEXT: [0x20,0x04,0x30,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x5f,0xf4,0x2f,0xd9]
|
||||
# NOMTE-NEXT: [0x41,0xf4,0x2f,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xe2,0x17,0x20,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xff,0x17,0x20,0xd9]
|
||||
|
||||
[0x3f,0x04,0x70,0xd9]
|
||||
[0x5f,0xf4,0x6f,0xd9]
|
||||
[0x20,0x04,0x70,0xd9]
|
||||
[0x41,0xf4,0x6f,0xd9]
|
||||
[0xe2,0x17,0x60,0xd9]
|
||||
[0xff,0x17,0x60,0xd9]
|
||||
|
||||
# CHECK: stzg [x1], #-4096
|
||||
# CHECK: stzg [x2], #4080
|
||||
# CHECK: stzg [sp], #16
|
||||
# CHECK: stzg x0, [x1], #-4096
|
||||
# CHECK: stzg x1, [x2], #4080
|
||||
# CHECK: stzg x2, [sp], #16
|
||||
# CHECK: stzg sp, [sp], #16
|
||||
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x3f,0x04,0x70,0xd9]
|
||||
# NOMTE-NEXT: [0x20,0x04,0x70,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x5f,0xf4,0x6f,0xd9]
|
||||
# NOMTE-NEXT: [0x41,0xf4,0x6f,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xe2,0x17,0x60,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xff,0x17,0x60,0xd9]
|
||||
|
||||
[0x3f,0x08,0xb0,0xd9]
|
||||
[0x5f,0xf8,0xaf,0xd9]
|
||||
[0xff,0x1b,0xa0,0xd9]
|
||||
[0x20,0x08,0xb0,0xd9]
|
||||
[0x41,0xf8,0xaf,0xd9]
|
||||
[0xe2,0x1b,0xa0,0xd9]
|
||||
[0x23,0x08,0xa0,0xd9]
|
||||
[0x3f,0x08,0xa0,0xd9]
|
||||
|
||||
# CHECK: st2g [x1, #-4096]
|
||||
# CHECK: st2g [x2, #4080]
|
||||
# CHECK: st2g [sp, #16]
|
||||
# CHECK: st2g [x1]
|
||||
# CHECK: st2g x0, [x1, #-4096]
|
||||
# CHECK: st2g x1, [x2, #4080]
|
||||
# CHECK: st2g x2, [sp, #16]
|
||||
# CHECK: st2g x3, [x1]
|
||||
# CHECK: st2g sp, [x1]
|
||||
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x3f,0x08,0xb0,0xd9]
|
||||
# NOMTE-NEXT: [0x20,0x08,0xb0,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x5f,0xf8,0xaf,0xd9]
|
||||
# NOMTE-NEXT: [0x41,0xf8,0xaf,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xff,0x1b,0xa0,0xd9]
|
||||
# NOMTE-NEXT: [0xe2,0x1b,0xa0,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x23,0x08,0xa0,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x3f,0x08,0xa0,0xd9]
|
||||
|
||||
[0x3f,0x08,0xf0,0xd9]
|
||||
[0x5f,0xf8,0xef,0xd9]
|
||||
[0xff,0x1b,0xe0,0xd9]
|
||||
[0x20,0x08,0xf0,0xd9]
|
||||
[0x41,0xf8,0xef,0xd9]
|
||||
[0xe2,0x1b,0xe0,0xd9]
|
||||
[0x23,0x08,0xe0,0xd9]
|
||||
[0x3f,0x08,0xe0,0xd9]
|
||||
|
||||
# CHECK: stz2g [x1, #-4096]
|
||||
# CHECK: stz2g [x2, #4080]
|
||||
# CHECK: stz2g [sp, #16]
|
||||
# CHECK: stz2g [x1]
|
||||
# CHECK: stz2g x0, [x1, #-4096]
|
||||
# CHECK: stz2g x1, [x2, #4080]
|
||||
# CHECK: stz2g x2, [sp, #16]
|
||||
# CHECK: stz2g x3, [x1]
|
||||
# CHECK: stz2g sp, [x1]
|
||||
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x3f,0x08,0xf0,0xd9]
|
||||
# NOMTE-NEXT: [0x20,0x08,0xf0,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x5f,0xf8,0xef,0xd9]
|
||||
# NOMTE-NEXT: [0x41,0xf8,0xef,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xff,0x1b,0xe0,0xd9]
|
||||
# NOMTE-NEXT: [0xe2,0x1b,0xe0,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x23,0x08,0xe0,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x3f,0x08,0xe0,0xd9]
|
||||
|
||||
[0x3f,0x0c,0xb0,0xd9]
|
||||
[0x5f,0xfc,0xaf,0xd9]
|
||||
[0x20,0x0c,0xb0,0xd9]
|
||||
[0x41,0xfc,0xaf,0xd9]
|
||||
[0xe2,0x1f,0xa0,0xd9]
|
||||
[0xff,0x1f,0xa0,0xd9]
|
||||
|
||||
# CHECK: st2g [x1, #-4096]!
|
||||
# CHECK: st2g [x2, #4080]!
|
||||
# CHECK: st2g [sp, #16]!
|
||||
# CHECK: st2g x0, [x1, #-4096]!
|
||||
# CHECK: st2g x1, [x2, #4080]!
|
||||
# CHECK: st2g x2, [sp, #16]!
|
||||
# CHECK: st2g sp, [sp, #16]!
|
||||
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x3f,0x0c,0xb0,0xd9]
|
||||
# NOMTE-NEXT: [0x20,0x0c,0xb0,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x5f,0xfc,0xaf,0xd9]
|
||||
# NOMTE-NEXT: [0x41,0xfc,0xaf,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xe2,0x1f,0xa0,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xff,0x1f,0xa0,0xd9]
|
||||
|
||||
[0x3f,0x0c,0xf0,0xd9]
|
||||
[0x5f,0xfc,0xef,0xd9]
|
||||
[0x20,0x0c,0xf0,0xd9]
|
||||
[0x41,0xfc,0xef,0xd9]
|
||||
[0xe2,0x1f,0xe0,0xd9]
|
||||
[0xff,0x1f,0xe0,0xd9]
|
||||
|
||||
# CHECK: stz2g [x1, #-4096]!
|
||||
# CHECK: stz2g [x2, #4080]!
|
||||
# CHECK: stz2g [sp, #16]!
|
||||
# CHECK: stz2g x0, [x1, #-4096]!
|
||||
# CHECK: stz2g x1, [x2, #4080]!
|
||||
# CHECK: stz2g x2, [sp, #16]!
|
||||
# CHECK: stz2g sp, [sp, #16]!
|
||||
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x3f,0x0c,0xf0,0xd9]
|
||||
# NOMTE-NEXT: [0x20,0x0c,0xf0,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x5f,0xfc,0xef,0xd9]
|
||||
# NOMTE-NEXT: [0x41,0xfc,0xef,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xe2,0x1f,0xe0,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xff,0x1f,0xe0,0xd9]
|
||||
|
||||
[0x3f,0x04,0xb0,0xd9]
|
||||
[0x5f,0xf4,0xaf,0xd9]
|
||||
[0x20,0x04,0xb0,0xd9]
|
||||
[0x41,0xf4,0xaf,0xd9]
|
||||
[0xe2,0x17,0xa0,0xd9]
|
||||
[0xff,0x17,0xa0,0xd9]
|
||||
|
||||
# CHECK: st2g [x1], #-4096
|
||||
# CHECK: st2g [x2], #4080
|
||||
# CHECK: st2g [sp], #16
|
||||
# CHECK: st2g x0, [x1], #-4096
|
||||
# CHECK: st2g x1, [x2], #4080
|
||||
# CHECK: st2g x2, [sp], #16
|
||||
# CHECK: st2g sp, [sp], #16
|
||||
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x3f,0x04,0xb0,0xd9]
|
||||
# NOMTE-NEXT: [0x20,0x04,0xb0,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x5f,0xf4,0xaf,0xd9]
|
||||
# NOMTE-NEXT: [0x41,0xf4,0xaf,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xe2,0x17,0xa0,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xff,0x17,0xa0,0xd9]
|
||||
|
||||
[0x3f,0x04,0xf0,0xd9]
|
||||
[0x5f,0xf4,0xef,0xd9]
|
||||
[0x20,0x04,0xf0,0xd9]
|
||||
[0x41,0xf4,0xef,0xd9]
|
||||
[0xe2,0x17,0xe0,0xd9]
|
||||
[0xff,0x17,0xe0,0xd9]
|
||||
|
||||
# CHECK: stz2g [x1], #-4096
|
||||
# CHECK: stz2g [x2], #4080
|
||||
# CHECK: stz2g [sp], #16
|
||||
# CHECK: stz2g x0, [x1], #-4096
|
||||
# CHECK: stz2g x1, [x2], #4080
|
||||
# CHECK: stz2g x2, [sp], #16
|
||||
# CHECK: stz2g sp, [sp], #16
|
||||
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x3f,0x04,0xf0,0xd9]
|
||||
# NOMTE-NEXT: [0x20,0x04,0xf0,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0x5f,0xf4,0xef,0xd9]
|
||||
# NOMTE-NEXT: [0x41,0xf4,0xef,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xe2,0x17,0xe0,0xd9]
|
||||
# NOMTE: warning: invalid instruction encoding
|
||||
# NOMTE-NEXT: [0xff,0x17,0xe0,0xd9]
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue