Remove the -disable-16bit command-line option, which is now obsolete.
llvm-svn: 102730
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408459ffa6
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57bb73c80b
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@ -57,14 +57,6 @@ STATISTIC(NumTailCalls, "Number of tail calls");
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static cl::opt<bool>
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static cl::opt<bool>
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DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
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DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
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// Disable16Bit - 16-bit operations typically have a larger encoding than
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// corresponding 32-bit instructions, and 16-bit code is slow on some
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// processors. This is an experimental flag to disable 16-bit operations
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// (which forces them to be Legalized to 32-bit operations).
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static cl::opt<bool>
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Disable16Bit("disable-16bit", cl::Hidden,
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cl::desc("Disable use of 16-bit instructions"));
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// Forward declarations.
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// Forward declarations.
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static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
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static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
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SDValue V2);
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SDValue V2);
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@ -120,8 +112,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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// Set up the register classes.
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// Set up the register classes.
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addRegisterClass(MVT::i8, X86::GR8RegisterClass);
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addRegisterClass(MVT::i8, X86::GR8RegisterClass);
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if (!Disable16Bit)
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addRegisterClass(MVT::i16, X86::GR16RegisterClass);
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addRegisterClass(MVT::i16, X86::GR16RegisterClass);
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addRegisterClass(MVT::i32, X86::GR32RegisterClass);
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addRegisterClass(MVT::i32, X86::GR32RegisterClass);
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if (Subtarget->is64Bit())
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if (Subtarget->is64Bit())
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addRegisterClass(MVT::i64, X86::GR64RegisterClass);
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addRegisterClass(MVT::i64, X86::GR64RegisterClass);
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@ -130,11 +121,9 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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// We don't accept any truncstore of integer registers.
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// We don't accept any truncstore of integer registers.
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setTruncStoreAction(MVT::i64, MVT::i32, Expand);
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setTruncStoreAction(MVT::i64, MVT::i32, Expand);
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if (!Disable16Bit)
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setTruncStoreAction(MVT::i64, MVT::i16, Expand);
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setTruncStoreAction(MVT::i64, MVT::i16, Expand);
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setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
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setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
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if (!Disable16Bit)
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setTruncStoreAction(MVT::i32, MVT::i16, Expand);
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setTruncStoreAction(MVT::i32, MVT::i16, Expand);
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setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
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setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
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setTruncStoreAction(MVT::i16, MVT::i8, Expand);
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setTruncStoreAction(MVT::i16, MVT::i8, Expand);
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@ -285,13 +274,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
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setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
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setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
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setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
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setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
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setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
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if (Disable16Bit) {
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setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
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setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
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setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
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setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
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} else {
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setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
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setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
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}
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setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
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setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
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setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
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setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
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setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
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@ -308,19 +292,13 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::SELECT , MVT::i1 , Promote);
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setOperationAction(ISD::SELECT , MVT::i1 , Promote);
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// X86 wants to expand cmov itself.
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// X86 wants to expand cmov itself.
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setOperationAction(ISD::SELECT , MVT::i8 , Custom);
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setOperationAction(ISD::SELECT , MVT::i8 , Custom);
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if (Disable16Bit)
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setOperationAction(ISD::SELECT , MVT::i16 , Custom);
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setOperationAction(ISD::SELECT , MVT::i16 , Expand);
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else
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setOperationAction(ISD::SELECT , MVT::i16 , Custom);
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setOperationAction(ISD::SELECT , MVT::i32 , Custom);
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setOperationAction(ISD::SELECT , MVT::i32 , Custom);
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setOperationAction(ISD::SELECT , MVT::f32 , Custom);
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setOperationAction(ISD::SELECT , MVT::f32 , Custom);
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setOperationAction(ISD::SELECT , MVT::f64 , Custom);
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setOperationAction(ISD::SELECT , MVT::f64 , Custom);
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setOperationAction(ISD::SELECT , MVT::f80 , Custom);
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setOperationAction(ISD::SELECT , MVT::f80 , Custom);
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setOperationAction(ISD::SETCC , MVT::i8 , Custom);
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setOperationAction(ISD::SETCC , MVT::i8 , Custom);
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if (Disable16Bit)
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setOperationAction(ISD::SETCC , MVT::i16 , Custom);
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setOperationAction(ISD::SETCC , MVT::i16 , Expand);
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else
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setOperationAction(ISD::SETCC , MVT::i16 , Custom);
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setOperationAction(ISD::SETCC , MVT::i32 , Custom);
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setOperationAction(ISD::SETCC , MVT::i32 , Custom);
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setOperationAction(ISD::SETCC , MVT::f32 , Custom);
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setOperationAction(ISD::SETCC , MVT::f32 , Custom);
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setOperationAction(ISD::SETCC , MVT::f64 , Custom);
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setOperationAction(ISD::SETCC , MVT::f64 , Custom);
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@ -2337,15 +2337,3 @@ let isTwoAddress = 1 in {
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}
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}
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defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
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defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
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// -disable-16bit support.
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def : Pat<(truncstorei16 (i16 imm:$src), addr:$dst),
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(MOV16mi addr:$dst, imm:$src)>;
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def : Pat<(truncstorei16 GR64:$src, addr:$dst),
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(MOV16mr addr:$dst, (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
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def : Pat<(i64 (sextloadi16 addr:$dst)),
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(MOVSX64rm16 addr:$dst)>;
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def : Pat<(i64 (zextloadi16 addr:$dst)),
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(MOVZX64rm16 addr:$dst)>;
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def : Pat<(i64 (extloadi16 addr:$dst)),
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(MOVZX64rm16 addr:$dst)>;
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@ -4792,18 +4792,6 @@ def : Pat<(and GR16:$src1, i16immSExt8:$src2),
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def : Pat<(and GR32:$src1, i32immSExt8:$src2),
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def : Pat<(and GR32:$src1, i32immSExt8:$src2),
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(AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
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(AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
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// -disable-16bit support.
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def : Pat<(truncstorei16 (i16 imm:$src), addr:$dst),
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(MOV16mi addr:$dst, imm:$src)>;
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def : Pat<(truncstorei16 GR32:$src, addr:$dst),
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(MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
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def : Pat<(i32 (sextloadi16 addr:$dst)),
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(MOVSX32rm16 addr:$dst)>;
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def : Pat<(i32 (zextloadi16 addr:$dst)),
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(MOVZX32rm16 addr:$dst)>;
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def : Pat<(i32 (extloadi16 addr:$dst)),
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(MOVZX32rm16 addr:$dst)>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Floating Point Stack Support
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// Floating Point Stack Support
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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