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AArch64/ARM64: rename ARM64 components to AArch64 

This keeps Clang consistent with backend naming conventions.

llvm-svn: 209579
This commit is contained in:
Tim Northover 2014-05-24 12:52:07 +00:00
parent 25e8a6754e
commit 573cbee543
31 changed files with 796 additions and 780 deletions
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2
clang/docs/LanguageExtensions.rst
View File

@ -1566,7 +1566,7 @@ instructions for implementing atomic operations.
void __builtin_arm_clrex(void);
The types ``T`` currently supported are:
* Integer types with width at most 64 bits (or 128 bits on ARM64).
* Integer types with width at most 64 bits (or 128 bits on AArch64).
* Floating-point types
* Pointer types.

4
clang/include/clang/Basic/BuiltinsARM64.def → clang/include/clang/Basic/BuiltinsAArch64.def
View File

@ -1,4 +1,4 @@
//===--- BuiltinsARM64.def - ARM64 Builtin function database ----*- C++ -*-===//
//==- BuiltinsAArch64.def - AArch64 Builtin function database ----*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
// This file defines the ARM64-specific builtin function database. Users of
// This file defines the AArch64-specific builtin function database. Users of
// this file must define the BUILTIN macro to make use of this information.
//
//===----------------------------------------------------------------------===//

6
clang/include/clang/Basic/TargetBuiltins.h
View File

@ -41,13 +41,13 @@ namespace clang {
};
}
/// \brief ARM64 builtins
namespace ARM64 {
/// \brief AArch64 builtins
namespace AArch64 {
enum {
LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1,
LastNEONBuiltin = NEON::FirstTSBuiltin - 1,
#define BUILTIN(ID, TYPE, ATTRS) BI##ID,
#include "clang/Basic/BuiltinsARM64.def"
#include "clang/Basic/BuiltinsAArch64.def"
LastTSBuiltin
};
}

2
clang/include/clang/Sema/Sema.h
View File

@ -8125,7 +8125,7 @@ private:
bool CheckNeonBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
bool CheckARMBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
bool CheckARM64BuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
bool CheckAArch64BuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
bool CheckMipsBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
bool CheckX86BuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);

68
clang/lib/Basic/Targets.cpp
View File

@ -4233,7 +4233,7 @@ public:
namespace {
class ARM64TargetInfo : public TargetInfo {
class AArch64TargetInfo : public TargetInfo {
virtual void setDescriptionString() = 0;
static const TargetInfo::GCCRegAlias GCCRegAliases[];
static const char *const GCCRegNames[];
@ -4252,7 +4252,7 @@ class ARM64TargetInfo : public TargetInfo {
std::string ABI;
public:
ARM64TargetInfo(const llvm::Triple &Triple)
AArch64TargetInfo(const llvm::Triple &Triple)
: TargetInfo(Triple), ABI("aapcs") {
if (getTriple().getOS() == llvm::Triple::NetBSD) {
@ -4283,7 +4283,7 @@ public:
// specifiers.
NoAsmVariants = true;
// ARM64 targets default to using the ARM C++ ABI.
// AArch64 targets default to using the ARM C++ ABI.
TheCXXABI.set(TargetCXXABI::GenericAArch64);
}
@ -4364,7 +4364,7 @@ public:
virtual void getTargetBuiltins(const Builtin::Info *&Records,
unsigned &NumRecords) const {
Records = BuiltinInfo;
NumRecords = clang::ARM64::LastTSBuiltin - Builtin::FirstTSBuiltin;
NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
}
virtual bool hasFeature(StringRef Feature) const {
@ -4453,7 +4453,7 @@ public:
}
};
const char *const ARM64TargetInfo::GCCRegNames[] = {
const char *const AArch64TargetInfo::GCCRegNames[] = {
// 32-bit Integer registers
"w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
"w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
@ -4480,13 +4480,13 @@ const char *const ARM64TargetInfo::GCCRegNames[] = {
"v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
};
void ARM64TargetInfo::getGCCRegNames(const char *const *&Names,
void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
unsigned &NumNames) const {
Names = GCCRegNames;
NumNames = llvm::array_lengthof(GCCRegNames);
}
const TargetInfo::GCCRegAlias ARM64TargetInfo::GCCRegAliases[] = {
const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
{ { "w31" }, "wsp" },
{ { "x29" }, "fp" },
{ { "x30" }, "lr" },
@ -4495,23 +4495,23 @@ const TargetInfo::GCCRegAlias ARM64TargetInfo::GCCRegAliases[] = {
// don't want to substitute one of these for a different-sized one.
};
void ARM64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
unsigned &NumAliases) const {
Aliases = GCCRegAliases;
NumAliases = llvm::array_lengthof(GCCRegAliases);
}
const Builtin::Info ARM64TargetInfo::BuiltinInfo[] = {
const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
#define BUILTIN(ID, TYPE, ATTRS) \
{ #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
#include "clang/Basic/BuiltinsNEON.def"
#define BUILTIN(ID, TYPE, ATTRS) \
{ #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
#include "clang/Basic/BuiltinsARM64.def"
#include "clang/Basic/BuiltinsAArch64.def"
};
class ARM64leTargetInfo : public ARM64TargetInfo {
class AArch64leTargetInfo : public AArch64TargetInfo {
void setDescriptionString() override {
if (getTriple().isOSBinFormatMachO())
DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
@ -4520,38 +4520,38 @@ class ARM64leTargetInfo : public ARM64TargetInfo {
}
public:
ARM64leTargetInfo(const llvm::Triple &Triple)
: ARM64TargetInfo(Triple) {
AArch64leTargetInfo(const llvm::Triple &Triple)
: AArch64TargetInfo(Triple) {
BigEndian = false;
}
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
Builder.defineMacro("__AARCH64EL__");
ARM64TargetInfo::getTargetDefines(Opts, Builder);
AArch64TargetInfo::getTargetDefines(Opts, Builder);
}
};
class ARM64beTargetInfo : public ARM64TargetInfo {
class AArch64beTargetInfo : public AArch64TargetInfo {
void setDescriptionString() override {
assert(!getTriple().isOSBinFormatMachO());
DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
}
public:
ARM64beTargetInfo(const llvm::Triple &Triple)
: ARM64TargetInfo(Triple) { }
AArch64beTargetInfo(const llvm::Triple &Triple)
: AArch64TargetInfo(Triple) { }
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
Builder.defineMacro("__AARCH64EB__");
Builder.defineMacro("__AARCH_BIG_ENDIAN");
Builder.defineMacro("__ARM_BIG_ENDIAN");
ARM64TargetInfo::getTargetDefines(Opts, Builder);
AArch64TargetInfo::getTargetDefines(Opts, Builder);
}
};
} // end anonymous namespace.
namespace {
class DarwinARM64TargetInfo : public DarwinTargetInfo<ARM64leTargetInfo> {
class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
protected:
void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
MacroBuilder &Builder) const override {
@ -4567,8 +4567,8 @@ protected:
}
public:
DarwinARM64TargetInfo(const llvm::Triple &Triple)
: DarwinTargetInfo<ARM64leTargetInfo>(Triple) {
DarwinAArch64TargetInfo(const llvm::Triple &Triple)
: DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
Int64Type = SignedLongLong;
WCharType = SignedInt;
UseSignedCharForObjCBool = false;
@ -5917,25 +5917,25 @@ static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
case llvm::Triple::arm64:
if (Triple.isOSDarwin())
return new DarwinARM64TargetInfo(Triple);
return new DarwinAArch64TargetInfo(Triple);
switch (os) {
case llvm::Triple::Linux:
return new LinuxTargetInfo<ARM64leTargetInfo>(Triple);
return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
case llvm::Triple::NetBSD:
return new NetBSDTargetInfo<ARM64leTargetInfo>(Triple);
return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
default:
return new ARM64leTargetInfo(Triple);
return new AArch64leTargetInfo(Triple);
}
case llvm::Triple::arm64_be:
switch (os) {
case llvm::Triple::Linux:
return new LinuxTargetInfo<ARM64beTargetInfo>(Triple);
return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
case llvm::Triple::NetBSD:
return new NetBSDTargetInfo<ARM64beTargetInfo>(Triple);
return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
default:
return new ARM64beTargetInfo(Triple);
return new AArch64beTargetInfo(Triple);
}
case llvm::Triple::xcore:
@ -5947,21 +5947,21 @@ static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
case llvm::Triple::aarch64:
switch (os) {
case llvm::Triple::Linux:
return new LinuxTargetInfo<ARM64leTargetInfo>(Triple);
return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
case llvm::Triple::NetBSD:
return new NetBSDTargetInfo<ARM64leTargetInfo>(Triple);
return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
default:
return new ARM64leTargetInfo(Triple);
return new AArch64leTargetInfo(Triple);
}
case llvm::Triple::aarch64_be:
switch (os) {
case llvm::Triple::Linux:
return new LinuxTargetInfo<ARM64beTargetInfo>(Triple);
return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
case llvm::Triple::NetBSD:
return new NetBSDTargetInfo<ARM64beTargetInfo>(Triple);
return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
default:
return new ARM64beTargetInfo(Triple);
return new AArch64beTargetInfo(Triple);
}
case llvm::Triple::arm:

902
clang/lib/CodeGen/CGBuiltin.cpp
View File

File diff suppressed because it is too large Load Diff

3
clang/lib/CodeGen/CGObjCMac.cpp
View File

@ -5034,7 +5034,8 @@ ObjCCommonTypesHelper::ObjCCommonTypesHelper(CodeGen::CodeGenModule &cgm)
// arm64 targets use "int" ivar offset variables. All others,
// including OS X x86_64 and Windows x86_64, use "long" ivar offsets.
if (CGM.getTarget().getTriple().getArch() == llvm::Triple::arm64)
if (CGM.getTarget().getTriple().getArch() == llvm::Triple::arm64 ||
CGM.getTarget().getTriple().getArch() == llvm::Triple::aarch64)
IvarOffsetVarTy = IntTy;
else
IvarOffsetVarTy = LongTy;

4
clang/lib/CodeGen/CodeGenFunction.h
View File

@ -2226,14 +2226,14 @@ public:
llvm::Value *EmitConcatVectors(llvm::Value *Lo, llvm::Value *Hi,
llvm::Type *ArgTy);
llvm::Value *EmitExtractHigh(llvm::Value *In, llvm::Type *ResTy);
// Helper functions for EmitARM64BuiltinExpr.
// Helper functions for EmitAArch64BuiltinExpr.
llvm::Value *vectorWrapScalar8(llvm::Value *Op);
llvm::Value *vectorWrapScalar16(llvm::Value *Op);
llvm::Value *emitVectorWrappedScalar8Intrinsic(
unsigned Int, SmallVectorImpl<llvm::Value *> &Ops, const char *Name);
llvm::Value *emitVectorWrappedScalar16Intrinsic(
unsigned Int, SmallVectorImpl<llvm::Value *> &Ops, const char *Name);
llvm::Value *EmitARM64BuiltinExpr(unsigned BuiltinID, const CallExpr *E);
llvm::Value *EmitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E);
llvm::Value *EmitNeon64Call(llvm::Function *F,
llvm::SmallVectorImpl<llvm::Value *> &O,
const char *name);

40
clang/lib/CodeGen/TargetInfo.cpp
View File

@ -3104,12 +3104,12 @@ PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
}
//===----------------------------------------------------------------------===//
// ARM64 ABI Implementation
// AArch64 ABI Implementation
//===----------------------------------------------------------------------===//
namespace {
class ARM64ABIInfo : public ABIInfo {
class AArch64ABIInfo : public ABIInfo {
public:
enum ABIKind {
AAPCS = 0,
@ -3120,7 +3120,7 @@ private:
ABIKind Kind;
public:
ARM64ABIInfo(CodeGenTypes &CGT, ABIKind Kind) : ABIInfo(CGT), Kind(Kind) {}
AArch64ABIInfo(CodeGenTypes &CGT, ABIKind Kind) : ABIInfo(CGT), Kind(Kind) {}
private:
ABIKind getABIKind() const { return Kind; }
@ -3212,10 +3212,10 @@ private:
}
};
class ARM64TargetCodeGenInfo : public TargetCodeGenInfo {
class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
public:
ARM64TargetCodeGenInfo(CodeGenTypes &CGT, ARM64ABIInfo::ABIKind Kind)
: TargetCodeGenInfo(new ARM64ABIInfo(CGT, Kind)) {}
AArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind Kind)
: TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
StringRef getARCRetainAutoreleasedReturnValueMarker() const {
return "mov\tfp, fp\t\t; marker for objc_retainAutoreleaseReturnValue";
@ -3231,12 +3231,12 @@ static bool isHomogeneousAggregate(QualType Ty, const Type *&Base,
ASTContext &Context,
uint64_t *HAMembers = nullptr);
ABIArgInfo ARM64ABIInfo::classifyArgumentType(QualType Ty,
unsigned &AllocatedVFP,
bool &IsHA,
unsigned &AllocatedGPR,
bool &IsSmallAggr,
bool IsNamedArg) const {
ABIArgInfo AArch64ABIInfo::classifyArgumentType(QualType Ty,
unsigned &AllocatedVFP,
bool &IsHA,
unsigned &AllocatedGPR,
bool &IsSmallAggr,
bool IsNamedArg) const {
// Handle illegal vector types here.
if (isIllegalVectorType(Ty)) {
uint64_t Size = getContext().getTypeSize(Ty);
@ -3346,7 +3346,7 @@ ABIArgInfo ARM64ABIInfo::classifyArgumentType(QualType Ty,
return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
}
ABIArgInfo ARM64ABIInfo::classifyReturnType(QualType RetTy) const {
ABIArgInfo AArch64ABIInfo::classifyReturnType(QualType RetTy) const {
if (RetTy->isVoidType())
return ABIArgInfo::getIgnore();
@ -3382,8 +3382,8 @@ ABIArgInfo ARM64ABIInfo::classifyReturnType(QualType RetTy) const {
return ABIArgInfo::getIndirect(0);
}
/// isIllegalVectorType - check whether the vector type is legal for ARM64.
bool ARM64ABIInfo::isIllegalVectorType(QualType Ty) const {
/// isIllegalVectorType - check whether the vector type is legal for AArch64.
bool AArch64ABIInfo::isIllegalVectorType(QualType Ty) const {
if (const VectorType *VT = Ty->getAs<VectorType>()) {
// Check whether VT is legal.
unsigned NumElements = VT->getNumElements();
@ -3624,7 +3624,7 @@ static llvm::Value *EmitAArch64VAArg(llvm::Value *VAListAddr, QualType Ty,
return ResAddr;
}
llvm::Value *ARM64ABIInfo::EmitAAPCSVAArg(llvm::Value *VAListAddr, QualType Ty,
llvm::Value *AArch64ABIInfo::EmitAAPCSVAArg(llvm::Value *VAListAddr, QualType Ty,
CodeGenFunction &CGF) const {
unsigned AllocatedGPR = 0, AllocatedVFP = 0;
@ -3636,7 +3636,7 @@ llvm::Value *ARM64ABIInfo::EmitAAPCSVAArg(llvm::Value *VAListAddr, QualType Ty,
AI.isIndirect(), CGF);
}
llvm::Value *ARM64ABIInfo::EmitDarwinVAArg(llvm::Value *VAListAddr, QualType Ty,
llvm::Value *AArch64ABIInfo::EmitDarwinVAArg(llvm::Value *VAListAddr, QualType Ty,
CodeGenFunction &CGF) const {
// We do not support va_arg for aggregates or illegal vector types.
// Lower VAArg here for these cases and use the LLVM va_arg instruction for
@ -6473,11 +6473,11 @@ const TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() {
case llvm::Triple::aarch64_be:
case llvm::Triple::arm64:
case llvm::Triple::arm64_be: {
ARM64ABIInfo::ABIKind Kind = ARM64ABIInfo::AAPCS;
AArch64ABIInfo::ABIKind Kind = AArch64ABIInfo::AAPCS;
if (strcmp(getTarget().getABI(), "darwinpcs") == 0)
Kind = ARM64ABIInfo::DarwinPCS;
Kind = AArch64ABIInfo::DarwinPCS;
return *(TheTargetCodeGenInfo = new ARM64TargetCodeGenInfo(Types, Kind));
return *(TheTargetCodeGenInfo = new AArch64TargetCodeGenInfo(Types, Kind));
}
case llvm::Triple::arm:

14
clang/lib/Driver/ToolChains.cpp
View File

@ -400,7 +400,8 @@ void DarwinClang::AddLinkRuntimeLibArgs(const ArgList &Args,
// it never went into the SDK.
// Linking against libgcc_s.1 isn't needed for iOS 5.0+
if (isIPhoneOSVersionLT(5, 0) && !isTargetIOSSimulator() &&
getTriple().getArch() != llvm::Triple::arm64)
(getTriple().getArch() != llvm::Triple::arm64 &&
getTriple().getArch() != llvm::Triple::aarch64))
CmdArgs.push_back("-lgcc_s.1");
// We currently always need a static runtime library for iOS.
@ -520,6 +521,7 @@ void Darwin::AddDeploymentTarget(DerivedArgList &Args) const {
if (!OSXTarget.empty() && !iOSTarget.empty()) {
if (getTriple().getArch() == llvm::Triple::arm ||
getTriple().getArch() == llvm::Triple::arm64 ||
getTriple().getArch() == llvm::Triple::aarch64 ||
getTriple().getArch() == llvm::Triple::thumb)
OSXTarget = "";
else
@ -656,6 +658,7 @@ void DarwinClang::AddCCKextLibArgs(const ArgList &Args,
// Use the newer cc_kext for iOS ARM after 6.0.
if (!isTargetIPhoneOS() || isTargetIOSSimulator() ||
getTriple().getArch() == llvm::Triple::arm64 ||
getTriple().getArch() == llvm::Triple::aarch64 ||
!isIPhoneOSVersionLT(6, 0)) {
llvm::sys::path::append(P, "libclang_rt.cc_kext.a");
} else {
@ -926,7 +929,8 @@ DerivedArgList *Darwin::TranslateArgs(const DerivedArgList &Args,
// but we can't check the deployment target in the translation code until
// it is set here.
if (isTargetIOSBased() && !isIPhoneOSVersionLT(6, 0) &&
getTriple().getArch() != llvm::Triple::arm64) {
getTriple().getArch() != llvm::Triple::arm64 &&
getTriple().getArch() != llvm::Triple::aarch64) {
for (ArgList::iterator it = DAL->begin(), ie = DAL->end(); it != ie; ) {
Arg *A = *it;
++it;
@ -993,7 +997,8 @@ bool MachO::isPIEDefault() const {
bool MachO::isPICDefaultForced() const {
return (getArch() == llvm::Triple::x86_64 ||
getArch() == llvm::Triple::arm64);
getArch() == llvm::Triple::arm64 ||
getArch() == llvm::Triple::aarch64);
}
bool MachO::SupportsProfiling() const {
@ -1082,7 +1087,8 @@ void Darwin::addStartObjectFileArgs(const llvm::opt::ArgList &Args,
if (isTargetIOSSimulator()) {
; // iOS simulator does not need crt1.o.
} else if (isTargetIPhoneOS()) {
if (getArch() == llvm::Triple::arm64)
if (getArch() == llvm::Triple::arm64 ||
getArch() == llvm::Triple::aarch64)
; // iOS does not need any crt1 files for arm64
else if (isIPhoneOSVersionLT(3, 1))
CmdArgs.push_back("-lcrt1.o");

34
clang/lib/Driver/Tools.cpp
View File

@ -841,8 +841,9 @@ void Clang::AddARMTargetArgs(const ArgList &Args,
}
}
/// getARM64TargetCPU - Get the (LLVM) name of the ARM64 cpu we are targeting.
static std::string getARM64TargetCPU(const ArgList &Args) {
/// getAArch64TargetCPU - Get the (LLVM) name of the AArch64 cpu we are
/// targeting.
static std::string getAArch64TargetCPU(const ArgList &Args) {
// If we have -mcpu=, use that.
if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
StringRef MCPU = A->getValue();
@ -864,8 +865,8 @@ static std::string getARM64TargetCPU(const ArgList &Args) {
return "generic";
}
void Clang::AddARM64TargetArgs(const ArgList &Args,
ArgStringList &CmdArgs) const {
void Clang::AddAArch64TargetArgs(const ArgList &Args,
ArgStringList &CmdArgs) const {
std::string TripleStr = getToolChain().ComputeEffectiveClangTriple(Args);
llvm::Triple Triple(TripleStr);
@ -890,11 +891,11 @@ void Clang::AddARM64TargetArgs(const ArgList &Args,
CmdArgs.push_back(ABIName);
CmdArgs.push_back("-target-cpu");
CmdArgs.push_back(Args.MakeArgString(getARM64TargetCPU(Args)));
CmdArgs.push_back(Args.MakeArgString(getAArch64TargetCPU(Args)));
if (Args.hasArg(options::OPT_mstrict_align)) {
CmdArgs.push_back("-backend-option");
CmdArgs.push_back("-arm64-strict-align");
CmdArgs.push_back("-aarch64-strict-align");
}
}
@ -1327,7 +1328,7 @@ static std::string getCPUName(const ArgList &Args, const llvm::Triple &T) {
case llvm::Triple::aarch64_be:
case llvm::Triple::arm64:
case llvm::Triple::arm64_be:
return getARM64TargetCPU(Args);
return getAArch64TargetCPU(Args);
case llvm::Triple::arm:
case llvm::Triple::armeb:
@ -2455,7 +2456,8 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
// PIC or PIE options above, if these show up, PIC is disabled.
llvm::Triple Triple(TripleStr);
if (KernelOrKext && (!Triple.isiOS() || Triple.isOSVersionLT(6) ||
Triple.getArch() == llvm::Triple::arm64))
Triple.getArch() == llvm::Triple::arm64 ||
Triple.getArch() == llvm::Triple::aarch64))
PIC = PIE = false;
if (Args.hasArg(options::OPT_static))
PIC = PIE = false;
@ -2782,9 +2784,11 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
AddARMTargetArgs(Args, CmdArgs, KernelOrKext);
break;
case llvm::Triple::aarch64:
case llvm::Triple::aarch64_be:
case llvm::Triple::arm64:
case llvm::Triple::arm64_be:
AddARM64TargetArgs(Args, CmdArgs);
AddAArch64TargetArgs(Args, CmdArgs);
break;
case llvm::Triple::mips:
@ -3408,16 +3412,20 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
options::OPT_munaligned_access)) {
if (A->getOption().matches(options::OPT_mno_unaligned_access)) {
CmdArgs.push_back("-backend-option");
if (getToolChain().getTriple().getArch() == llvm::Triple::arm64 ||
if (getToolChain().getTriple().getArch() == llvm::Triple::aarch64 ||
getToolChain().getTriple().getArch() == llvm::Triple::aarch64_be ||
getToolChain().getTriple().getArch() == llvm::Triple::arm64 ||
getToolChain().getTriple().getArch() == llvm::Triple::arm64_be)
CmdArgs.push_back("-arm64-strict-align");
CmdArgs.push_back("-aarch64-strict-align");
else
CmdArgs.push_back("-arm-strict-align");
} else {
CmdArgs.push_back("-backend-option");
if (getToolChain().getTriple().getArch() == llvm::Triple::arm64 ||
if (getToolChain().getTriple().getArch() == llvm::Triple::aarch64 ||
getToolChain().getTriple().getArch() == llvm::Triple::aarch64_be ||
getToolChain().getTriple().getArch() == llvm::Triple::arm64 ||
getToolChain().getTriple().getArch() == llvm::Triple::arm64_be)
CmdArgs.push_back("-arm64-no-strict-align");
CmdArgs.push_back("-aarch64-no-strict-align");
else
CmdArgs.push_back("-arm-no-strict-align");
}

1
clang/lib/Frontend/InitHeaderSearch.cpp
View File

@ -379,6 +379,7 @@ AddDefaultCPlusPlusIncludePaths(const llvm::Triple &triple, const HeaderSearchOp
"arm-apple-darwin10", "v6", "", triple);
break;
case llvm::Triple::aarch64:
case llvm::Triple::arm64:
AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.2.1",
"arm64-apple-darwin10", "", "", triple);

14
clang/lib/Sema/SemaChecking.cpp
View File

@ -313,7 +313,7 @@ Sema::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
case llvm::Triple::aarch64_be:
case llvm::Triple::arm64:
case llvm::Triple::arm64_be:
if (CheckARM64BuiltinFunctionCall(BuiltinID, TheCall))
if (CheckAArch64BuiltinFunctionCall(BuiltinID, TheCall))
return ExprError();
break;
case llvm::Triple::mips:
@ -473,11 +473,11 @@ bool Sema::CheckARMBuiltinExclusiveCall(unsigned BuiltinID, CallExpr *TheCall,
unsigned MaxWidth) {
assert((BuiltinID == ARM::BI__builtin_arm_ldrex ||
BuiltinID == ARM::BI__builtin_arm_strex ||
BuiltinID == ARM64::BI__builtin_arm_ldrex ||
BuiltinID == ARM64::BI__builtin_arm_strex) &&
BuiltinID == AArch64::BI__builtin_arm_ldrex ||
BuiltinID == AArch64::BI__builtin_arm_strex) &&
"unexpected ARM builtin");
bool IsLdrex = BuiltinID == ARM::BI__builtin_arm_ldrex ||
BuiltinID == ARM64::BI__builtin_arm_ldrex;
BuiltinID == AArch64::BI__builtin_arm_ldrex;
DeclRefExpr *DRE =cast<DeclRefExpr>(TheCall->getCallee()->IgnoreParenCasts());
@ -608,12 +608,12 @@ bool Sema::CheckARMBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
return SemaBuiltinConstantArgRange(TheCall, i, l, u + l);
}
bool Sema::CheckARM64BuiltinFunctionCall(unsigned BuiltinID,
bool Sema::CheckAArch64BuiltinFunctionCall(unsigned BuiltinID,
CallExpr *TheCall) {
llvm::APSInt Result;
if (BuiltinID == ARM64::BI__builtin_arm_ldrex ||
BuiltinID == ARM64::BI__builtin_arm_strex) {
if (BuiltinID == AArch64::BI__builtin_arm_ldrex ||
BuiltinID == AArch64::BI__builtin_arm_strex) {
return CheckARMBuiltinExclusiveCall(BuiltinID, TheCall, 128);
}

16
clang/test/CodeGen/arm64-crc32.c
View File

@ -6,50 +6,50 @@ int crc32b(int a, char b)
{
return __builtin_arm_crc32b(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
// CHECK: call i32 @llvm.arm64.crc32b(i32 %a, i32 [[T0]])
// CHECK: call i32 @llvm.aarch64.crc32b(i32 %a, i32 [[T0]])
}
int crc32cb(int a, char b)
{
return __builtin_arm_crc32cb(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
// CHECK: call i32 @llvm.arm64.crc32cb(i32 %a, i32 [[T0]])
// CHECK: call i32 @llvm.aarch64.crc32cb(i32 %a, i32 [[T0]])
}
int crc32h(int a, short b)
{
return __builtin_arm_crc32h(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32
// CHECK: call i32 @llvm.arm64.crc32h(i32 %a, i32 [[T0]])
// CHECK: call i32 @llvm.aarch64.crc32h(i32 %a, i32 [[T0]])
}
int crc32ch(int a, short b)
{
return __builtin_arm_crc32ch(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32
// CHECK: call i32 @llvm.arm64.crc32ch(i32 %a, i32 [[T0]])
// CHECK: call i32 @llvm.aarch64.crc32ch(i32 %a, i32 [[T0]])
}
int crc32w(int a, int b)
{
return __builtin_arm_crc32w(a,b);
// CHECK: call i32 @llvm.arm64.crc32w(i32 %a, i32 %b)
// CHECK: call i32 @llvm.aarch64.crc32w(i32 %a, i32 %b)
}
int crc32cw(int a, int b)
{
return __builtin_arm_crc32cw(a,b);
// CHECK: call i32 @llvm.arm64.crc32cw(i32 %a, i32 %b)
// CHECK: call i32 @llvm.aarch64.crc32cw(i32 %a, i32 %b)
}
int crc32d(int a, long b)
{
return __builtin_arm_crc32d(a,b);
// CHECK: call i32 @llvm.arm64.crc32x(i32 %a, i64 %b)
// CHECK: call i32 @llvm.aarch64.crc32x(i32 %a, i64 %b)
}
int crc32cd(int a, long b)
{
return __builtin_arm_crc32cd(a,b);
// CHECK: call i32 @llvm.arm64.crc32cx(i32 %a, i64 %b)
// CHECK: call i32 @llvm.aarch64.crc32cx(i32 %a, i64 %b)
}

8
clang/test/CodeGen/arm64-vrnd.c
View File

@ -11,13 +11,13 @@ int64x2_t rnd5(float64x2_t a) { return vrndq_f64(a); }
int32x2_t rnd7(float32x2_t a) { return vrndn_f32(a); }
// CHECK: call <2 x float> @llvm.arm64.neon.frintn.v2f32(<2 x float>
// CHECK: call <2 x float> @llvm.aarch64.neon.frintn.v2f32(<2 x float>
int32x4_t rnd8(float32x4_t a) { return vrndnq_f32(a); }
// CHECK: call <4 x float> @llvm.arm64.neon.frintn.v4f32(<4 x float>
// CHECK: call <4 x float> @llvm.aarch64.neon.frintn.v4f32(<4 x float>
int64x2_t rnd9(float64x2_t a) { return vrndnq_f64(a); }
// CHECK: call <2 x double> @llvm.arm64.neon.frintn.v2f64(<2 x double>
// CHECK: call <2 x double> @llvm.aarch64.neon.frintn.v2f64(<2 x double>
int64x2_t rnd10(float64x2_t a) { return vrndnq_f64(a); }
// CHECK: call <2 x double> @llvm.arm64.neon.frintn.v2f64(<2 x double>
// CHECK: call <2 x double> @llvm.aarch64.neon.frintn.v2f64(<2 x double>
int32x2_t rnd11(float32x2_t a) { return vrndm_f32(a); }
// CHECK: call <2 x float> @llvm.floor.v2f32(<2 x float>

12
clang/test/CodeGen/arm64-vrsqrt.c
View File

@ -4,40 +4,40 @@
uint32x2_t test_vrsqrte_u32(uint32x2_t in) {
// CHECK-LABEL: @test_vrsqrte_u32
// CHECK: call <2 x i32> @llvm.arm64.neon.ursqrte.v2i32(<2 x i32> %in)
// CHECK: call <2 x i32> @llvm.aarch64.neon.ursqrte.v2i32(<2 x i32> %in)
return vrsqrte_u32(in);
}
float32x2_t test_vrsqrte_f32(float32x2_t in) {
// CHECK-LABEL: @test_vrsqrte_f32
// CHECK: call <2 x float> @llvm.arm64.neon.frsqrte.v2f32(<2 x float> %in)
// CHECK: call <2 x float> @llvm.aarch64.neon.frsqrte.v2f32(<2 x float> %in)
return vrsqrte_f32(in);
}
uint32x4_t test_vrsqrteq_u32(uint32x4_t in) {
// CHECK-LABEL: @test_vrsqrteq_u32
// CHECK: call <4 x i32> @llvm.arm64.neon.ursqrte.v4i32(<4 x i32> %in)
// CHECK: call <4 x i32> @llvm.aarch64.neon.ursqrte.v4i32(<4 x i32> %in)
return vrsqrteq_u32(in);
}
float32x4_t test_vrsqrteq_f32(float32x4_t in) {
// CHECK-LABEL: @test_vrsqrteq_f32
// CHECK: call <4 x float> @llvm.arm64.neon.frsqrte.v4f32(<4 x float> %in)
// CHECK: call <4 x float> @llvm.aarch64.neon.frsqrte.v4f32(<4 x float> %in)
return vrsqrteq_f32(in);
}
float32x2_t test_vrsqrts_f32(float32x2_t est, float32x2_t val) {
// CHECK-LABEL: @test_vrsqrts_f32
// CHECK: call <2 x float> @llvm.arm64.neon.frsqrts.v2f32(<2 x float> %est, <2 x float> %val)
// CHECK: call <2 x float> @llvm.aarch64.neon.frsqrts.v2f32(<2 x float> %est, <2 x float> %val)
return vrsqrts_f32(est, val);
}
float32x4_t test_vrsqrtsq_f32(float32x4_t est, float32x4_t val) {
// CHECK-LABEL: @test_vrsqrtsq_f32
// CHECK: call <4 x float> @llvm.arm64.neon.frsqrts.v4f32(<4 x float> %est, <4 x float> %val)
// CHECK: call <4 x float> @llvm.aarch64.neon.frsqrts.v4f32(<4 x float> %est, <4 x float> %val)
return vrsqrtsq_f32(est, val);
}

4
clang/test/CodeGen/arm64_vCMP.c
View File

@ -7,7 +7,7 @@
int64x2_t test_vabsq_s64(int64x2_t a1) {
// CHECK: test_vabsq_s64
return vabsq_s64(a1);
// CHECK: llvm.arm64.neon.abs.v2i64
// CHECK: llvm.aarch64.neon.abs.v2i64
// CHECK-NEXT: ret
}
@ -103,6 +103,6 @@ uint64x2_t test_vcltq_u64(uint64x2_t a1, uint64x2_t a2) {
int64x2_t test_vqabsq_s64(int64x2_t a1) {
// CHECK: test_vqabsq_s64
return vqabsq_s64(a1);
// CHECK: llvm.arm64.neon.sqabs.v2i64(<2 x i64> %a1)
// CHECK: llvm.aarch64.neon.sqabs.v2i64(<2 x i64> %a1)
// CHECK-NEXT: ret
}

40
clang/test/CodeGen/arm64_vLdStNum_lane.c
View File

@ -6,25 +6,25 @@
int64x2x2_t test_vld2q_lane_s64(const void * a1, int64x2x2_t a2) {
// CHECK: test_vld2q_lane_s64
return vld2q_lane_s64(a1, a2, 1);
// CHECK: llvm.arm64.neon.ld2lane.v2i64.p0i8
// CHECK: llvm.aarch64.neon.ld2lane.v2i64.p0i8
}
uint64x2x2_t test_vld2q_lane_u64(const void * a1, uint64x2x2_t a2) {
// CHECK: test_vld2q_lane_u64
return vld2q_lane_u64(a1, a2, 1);
// CHECK: llvm.arm64.neon.ld2lane.v2i64.p0i8
// CHECK: llvm.aarch64.neon.ld2lane.v2i64.p0i8
}
int64x1x2_t test_vld2_lane_s64(const void * a1, int64x1x2_t a2) {
// CHECK: test_vld2_lane_s64
return vld2_lane_s64(a1, a2, 0);
// CHECK: llvm.arm64.neon.ld2lane.v1i64.p0i8
// CHECK: llvm.aarch64.neon.ld2lane.v1i64.p0i8
}
uint64x1x2_t test_vld2_lane_u64(const void * a1, uint64x1x2_t a2) {
// CHECK: test_vld2_lane_u64
return vld2_lane_u64(a1, a2, 0);
// CHECK: llvm.arm64.neon.ld2lane.v1i64.p0i8
// CHECK: llvm.aarch64.neon.ld2lane.v1i64.p0i8
}
poly8x16x2_t test_vld2q_lane_p8(const void * a1, poly8x16x2_t a2) {
@ -37,91 +37,91 @@ poly8x16x2_t test_vld2q_lane_p8(const void * a1, poly8x16x2_t a2) {
uint8x16x2_t test_vld2q_lane_u8(const void * a1, uint8x16x2_t a2) {
// CHECK: test_vld2q_lane_u8
return vld2q_lane_u8(a1, a2, 0);
// CHECK: llvm.arm64.neon.ld2lane.v16i8.p0i8
// CHECK: llvm.aarch64.neon.ld2lane.v16i8.p0i8
}
int64x2x3_t test_vld3q_lane_s64(const void * a1, int64x2x3_t a2) {
// CHECK: test_vld3q_lane_s64
return vld3q_lane_s64(a1, a2, 1);
// CHECK: llvm.arm64.neon.ld3lane.v2i64.p0i8
// CHECK: llvm.aarch64.neon.ld3lane.v2i64.p0i8
}
uint64x2x3_t test_vld3q_lane_u64(const void * a1, uint64x2x3_t a2) {
// CHECK: test_vld3q_lane_u64
return vld3q_lane_u64(a1, a2, 1);
// CHECK: llvm.arm64.neon.ld3lane.v2i64.p0i8
// CHECK: llvm.aarch64.neon.ld3lane.v2i64.p0i8
}
int64x1x3_t test_vld3_lane_s64(const void * a1, int64x1x3_t a2) {
// CHECK: test_vld3_lane_s64
return vld3_lane_s64(a1, a2, 0);
// CHECK: llvm.arm64.neon.ld3lane.v1i64.p0i8
// CHECK: llvm.aarch64.neon.ld3lane.v1i64.p0i8
}
uint64x1x3_t test_vld3_lane_u64(const void * a1, uint64x1x3_t a2) {
// CHECK: test_vld3_lane_u64
return vld3_lane_u64(a1, a2, 0);
// CHECK: llvm.arm64.neon.ld3lane.v1i64.p0i8
// CHECK: llvm.aarch64.neon.ld3lane.v1i64.p0i8
}
int8x8x3_t test_vld3_lane_s8(const void * a1, int8x8x3_t a2) {
// CHECK: test_vld3_lane_s8
return vld3_lane_s8(a1, a2, 0);
// CHECK: llvm.arm64.neon.ld3lane.v8i8.p0i8
// CHECK: llvm.aarch64.neon.ld3lane.v8i8.p0i8
}
poly8x16x3_t test_vld3q_lane_p8(const void * a1, poly8x16x3_t a2) {
// CHECK: test_vld3q_lane_p8
return vld3q_lane_p8(a1, a2, 0);
// CHECK: llvm.arm64.neon.ld3lane.v16i8.p0i8
// CHECK: llvm.aarch64.neon.ld3lane.v16i8.p0i8
}
uint8x16x3_t test_vld3q_lane_u8(const void * a1, uint8x16x3_t a2) {
// CHECK: test_vld3q_lane_u8
return vld3q_lane_u8(a1, a2, 0);
// CHECK: llvm.arm64.neon.ld3lane.v16i8.p0i8
// CHECK: llvm.aarch64.neon.ld3lane.v16i8.p0i8
}
int64x2x4_t test_vld4q_lane_s64(const void * a1, int64x2x4_t a2) {
// CHECK: test_vld4q_lane_s64
return vld4q_lane_s64(a1, a2, 0);
// CHECK: llvm.arm64.neon.ld4lane.v2i64.p0i8
// CHECK: llvm.aarch64.neon.ld4lane.v2i64.p0i8
}
uint64x2x4_t test_vld4q_lane_u64(const void * a1, uint64x2x4_t a2) {
// CHECK: test_vld4q_lane_u64
return vld4q_lane_u64(a1, a2, 0);
// CHECK: llvm.arm64.neon.ld4lane.v2i64.p0i8
// CHECK: llvm.aarch64.neon.ld4lane.v2i64.p0i8
}
int64x1x4_t test_vld4_lane_s64(const void * a1, int64x1x4_t a2) {
// CHECK: test_vld4_lane_s64
return vld4_lane_s64(a1, a2, 0);
// CHECK: llvm.arm64.neon.ld4lane.v1i64.p0i8
// CHECK: llvm.aarch64.neon.ld4lane.v1i64.p0i8
}
uint64x1x4_t test_vld4_lane_u64(const void * a1, uint64x1x4_t a2) {
// CHECK: test_vld4_lane_u64
return vld4_lane_u64(a1, a2, 0);
// CHECK: llvm.arm64.neon.ld4lane.v1i64.p0i8
// CHECK: llvm.aarch64.neon.ld4lane.v1i64.p0i8
}
int8x8x4_t test_vld4_lane_s8(const void * a1, int8x8x4_t a2) {
// CHECK: test_vld4_lane_s8
return vld4_lane_s8(a1, a2, 0);
// CHECK: llvm.arm64.neon.ld4lane.v8i8.p0i8
// CHECK: llvm.aarch64.neon.ld4lane.v8i8.p0i8
}
uint8x8x4_t test_vld4_lane_u8(const void * a1, uint8x8x4_t a2) {
// CHECK: test_vld4_lane_u8
return vld4_lane_u8(a1, a2, 0);
// CHECK: llvm.arm64.neon.ld4lane.v8i8.p0i8
// CHECK: llvm.aarch64.neon.ld4lane.v8i8.p0i8
}
poly8x16x4_t test_vld4q_lane_p8(const void * a1, poly8x16x4_t a2) {
// CHECK: test_vld4q_lane_p8
return vld4q_lane_p8(a1, a2, 0);
// CHECK: llvm.arm64.neon.ld4lane.v16i8.p0i8
// CHECK: llvm.aarch64.neon.ld4lane.v16i8.p0i8
}
int8x16x4_t test_vld4q_lane_s8(const void * a1, int8x16x4_t a2) {
@ -136,6 +136,6 @@ int8x16x4_t test_vld4q_lane_s8(const void * a1, int8x16x4_t a2) {
uint8x16x4_t test_vld4q_lane_u8(const void * a1, uint8x16x4_t a2) {
// CHECK: test_vld4q_lane_u8
return vld4q_lane_u8(a1, a2, 0);
// CHECK: llvm.arm64.neon.ld4lane.v16i8.p0i8
// CHECK: llvm.aarch64.neon.ld4lane.v16i8.p0i8
}

54
clang/test/CodeGen/arm64_vMaxMin.c
View File

@ -9,75 +9,75 @@
int8_t test_vmaxv_s8(int8x8_t a1) {
// CHECK: test_vmaxv_s8
return vmaxv_s8(a1);
// CHECK @llvm.arm64.neon.smaxv.i32.v8i8
// CHECK @llvm.aarch64.neon.smaxv.i32.v8i8
}
uint16_t test_vminvq_u16(uint16x8_t a1) {
// CHECK: test_vminvq_u16
return vminvq_u16(a1);
// CHECK llvm.arm64.neon.uminv.i16.v8i16
// CHECK llvm.aarch64.neon.uminv.i16.v8i16
}
// Test a represntative sample of 8 and 16, signed and unsigned, 64 and 128 bit pairwise
uint8x8_t test_vmin_u8(uint8x8_t a1, uint8x8_t a2) {
// CHECK: test_vmin_u8
return vmin_u8(a1, a2);
// CHECK llvm.arm64.neon.umin.v8i8
// CHECK llvm.aarch64.neon.umin.v8i8
}
uint8x16_t test_vminq_u8(uint8x16_t a1, uint8x16_t a2) {
// CHECK: test_vminq_u8
return vminq_u8(a1, a2);
// CHECK llvm.arm64.neon.umin.v16i8
// CHECK llvm.aarch64.neon.umin.v16i8
}
int16x8_t test_vmaxq_s16(int16x8_t a1, int16x8_t a2) {
// CHECK: test_vmaxq_s16
return vmaxq_s16(a1, a2);
// CHECK llvm.arm64.neon.smax.v8i16
// CHECK llvm.aarch64.neon.smax.v8i16
}
// Test the more complicated cases of [suf]32 and f64
float64x2_t test_vmaxq_f64(float64x2_t a1, float64x2_t a2) {
// CHECK: test_vmaxq_f64
return vmaxq_f64(a1, a2);
// CHECK llvm.arm64.neon.fmax.v2f64
// CHECK llvm.aarch64.neon.fmax.v2f64
}
float32x4_t test_vmaxq_f32(float32x4_t a1, float32x4_t a2) {
// CHECK: test_vmaxq_f32
return vmaxq_f32(a1, a2);
// CHECK llvm.arm64.neon.fmax.v4f32
// CHECK llvm.aarch64.neon.fmax.v4f32
}
float64x2_t test_vminq_f64(float64x2_t a1, float64x2_t a2) {
// CHECK: test_vminq_f64
return vminq_f64(a1, a2);
// CHECK llvm.arm64.neon.fmin.v2f64
// CHECK llvm.aarch64.neon.fmin.v2f64
}
float32x2_t test_vmax_f32(float32x2_t a1, float32x2_t a2) {
// CHECK: test_vmax_f32
return vmax_f32(a1, a2);
// CHECK llvm.arm64.neon.fmax.v2f32
// CHECK llvm.aarch64.neon.fmax.v2f32
}
int32x2_t test_vmax_s32(int32x2_t a1, int32x2_t a2) {
// CHECK: test_vmax_s32
return vmax_s32(a1, a2);
// CHECK llvm.arm64.neon.smax.v2i32
// CHECK llvm.aarch64.neon.smax.v2i32
}
uint32x2_t test_vmin_u32(uint32x2_t a1, uint32x2_t a2) {
// CHECK: test_vmin_u32
return vmin_u32(a1, a2);
// CHECK llvm.arm64.neon.umin.v2i32
// CHECK llvm.aarch64.neon.umin.v2i32
}
float32_t test_vmaxnmv_f32(float32x2_t a1) {
// CHECK: test_vmaxnmv_f32
return vmaxnmv_f32(a1);
// CHECK: llvm.arm64.neon.fmaxnmv.f32.v2f32
// CHECK: llvm.aarch64.neon.fmaxnmv.f32.v2f32
// CHECK-NEXT: ret
}
@ -87,7 +87,7 @@ float32_t test_vmaxnmv_f32(float32x2_t a1) {
float64_t test_vmaxnmvq_f64(float64x2_t a1) {
// CHECK@ test_vmaxnmvq_f64
return vmaxnmvq_f64(a1);
// CHECK@ llvm.arm64.neon.saddlv.i64.v2i32
// CHECK@ llvm.aarch64.neon.saddlv.i64.v2i32
// CHECK-NEXT@ ret
}
#endif
@ -95,14 +95,14 @@ float64_t test_vmaxnmvq_f64(float64x2_t a1) {
float32_t test_vmaxnmvq_f32(float32x4_t a1) {
// CHECK: test_vmaxnmvq_f32
return vmaxnmvq_f32(a1);
// CHECK: llvm.arm64.neon.fmaxnmv.f32.v4f32
// CHECK: llvm.aarch64.neon.fmaxnmv.f32.v4f32
// CHECK-NEXT: ret
}
float32_t test_vmaxv_f32(float32x2_t a1) {
// CHECK: test_vmaxv_f32
return vmaxv_f32(a1);
// CHECK: llvm.arm64.neon.fmaxv.f32.v2f32
// CHECK: llvm.aarch64.neon.fmaxv.f32.v2f32
// FIXME check that the 2nd and 3rd arguments are the same V register below
// CHECK-CODEGEN: fmaxp.2s
// CHECK-NEXT: ret
@ -111,7 +111,7 @@ float32_t test_vmaxv_f32(float32x2_t a1) {
int32_t test_vmaxv_s32(int32x2_t a1) {
// CHECK: test_vmaxv_s32
return vmaxv_s32(a1);
// CHECK: llvm.arm64.neon.smaxv.i32.v2i32
// CHECK: llvm.aarch64.neon.smaxv.i32.v2i32
// FIXME check that the 2nd and 3rd arguments are the same V register below
// CHECK-CODEGEN: smaxp.2s
// CHECK-NEXT: ret
@ -120,7 +120,7 @@ int32_t test_vmaxv_s32(int32x2_t a1) {
uint32_t test_vmaxv_u32(uint32x2_t a1) {
// CHECK: test_vmaxv_u32
return vmaxv_u32(a1);
// CHECK: llvm.arm64.neon.umaxv.i32.v2i32
// CHECK: llvm.aarch64.neon.umaxv.i32.v2i32
// FIXME check that the 2nd and 3rd arguments are the same V register below
// CHECK-CODEGEN: umaxp.2s
// CHECK-NEXT: ret
@ -131,7 +131,7 @@ uint32_t test_vmaxv_u32(uint32x2_t a1) {
float64_t test_vmaxvq_f64(float64x2_t a1) {
// CHECK@ test_vmaxvq_f64
return vmaxvq_f64(a1);
// CHECK@ llvm.arm64.neon.fmaxv.i64.v2f64
// CHECK@ llvm.aarch64.neon.fmaxv.i64.v2f64
// CHECK-NEXT@ ret
}
#endif
@ -139,21 +139,21 @@ float64_t test_vmaxvq_f64(float64x2_t a1) {
float32_t test_vmaxvq_f32(float32x4_t a1) {
// CHECK: test_vmaxvq_f32
return vmaxvq_f32(a1);
// CHECK: llvm.arm64.neon.fmaxv.f32.v4f32
// CHECK: llvm.aarch64.neon.fmaxv.f32.v4f32
// CHECK-NEXT: ret
}
float32_t test_vminnmv_f32(float32x2_t a1) {
// CHECK: test_vminnmv_f32
return vminnmv_f32(a1);
// CHECK: llvm.arm64.neon.fminnmv.f32.v2f32
// CHECK: llvm.aarch64.neon.fminnmv.f32.v2f32
// CHECK-NEXT: ret
}
float32_t test_vminvq_f32(float32x4_t a1) {
// CHECK: test_vminvq_f32
return vminvq_f32(a1);
// CHECK: llvm.arm64.neon.fminv.f32.v4f32
// CHECK: llvm.aarch64.neon.fminv.f32.v4f32
// CHECK-NEXT: ret
}
@ -163,7 +163,7 @@ float32_t test_vminvq_f32(float32x4_t a1) {
float64_t test_vminnmvq_f64(float64x2_t a1) {
// CHECK@ test_vminnmvq_f64
return vminnmvq_f64(a1);
// CHECK@ llvm.arm64.neon.saddlv.i64.v2i32
// CHECK@ llvm.aarch64.neon.saddlv.i64.v2i32
// CHECK-NEXT@ ret
}
#endif
@ -171,21 +171,21 @@ float64_t test_vminnmvq_f64(float64x2_t a1) {
float32_t test_vminnmvq_f32(float32x4_t a1) {
// CHECK: test_vminnmvq_f32
return vminnmvq_f32(a1);
// CHECK: llvm.arm64.neon.fminnmv.f32.v4f32
// CHECK: llvm.aarch64.neon.fminnmv.f32.v4f32
// CHECK-NEXT: ret
}
float32_t test_vminv_f32(float32x2_t a1) {
// CHECK: test_vminv_f32
return vminv_f32(a1);
// CHECK: llvm.arm64.neon.fminv.f32.v2f32
// CHECK: llvm.aarch64.neon.fminv.f32.v2f32
// CHECK-NEXT: ret
}
int32_t test_vminv_s32(int32x2_t a1) {
// CHECK: test_vminv_s32
return vminv_s32(a1);
// CHECK: llvm.arm64.neon.sminv.i32.v2i32
// CHECK: llvm.aarch64.neon.sminv.i32.v2i32
// CHECK-CODEGEN: sminp.2s
// CHECK-NEXT: ret
}
@ -193,7 +193,7 @@ int32_t test_vminv_s32(int32x2_t a1) {
uint32_t test_vminv_u32(uint32x2_t a1) {
// CHECK: test_vminv_u32
return vminv_u32(a1);
// CHECK: llvm.arm64.neon.fminv.f32.v2f32
// CHECK: llvm.aarch64.neon.fminv.f32.v2f32
}
// FIXME punt on this for now; don't forget to fix CHECKs
@ -201,7 +201,7 @@ uint32_t test_vminv_u32(uint32x2_t a1) {
float64_t test_vminvq_f64(float64x2_t a1) {
// CHECK@ test_vminvq_f64
return vminvq_f64(a1);
// CHECK@ llvm.arm64.neon.saddlv.i64.v2i32
// CHECK@ llvm.aarch64.neon.saddlv.i64.v2i32
// CHECK-NEXT@ ret
}
#endif

28
clang/test/CodeGen/arm64_vadd.c
View File

@ -5,98 +5,98 @@
int64_t test_vaddlv_s32(int32x2_t a1) {
// CHECK: test_vaddlv_s32
return vaddlv_s32(a1);
// CHECK: llvm.arm64.neon.saddlv.i64.v2i32
// CHECK: llvm.aarch64.neon.saddlv.i64.v2i32
// CHECK-NEXT: ret
}
uint64_t test_vaddlv_u32(uint32x2_t a1) {
// CHECK: test_vaddlv_u32
return vaddlv_u32(a1);
// CHECK: llvm.arm64.neon.uaddlv.i64.v2i32
// CHECK: llvm.aarch64.neon.uaddlv.i64.v2i32
// CHECK-NEXT: ret
}
int8_t test_vaddv_s8(int8x8_t a1) {
// CHECK: test_vaddv_s8
return vaddv_s8(a1);
// CHECK: llvm.arm64.neon.saddv.i32.v8i8
// CHECK: llvm.aarch64.neon.saddv.i32.v8i8
// don't check for return here (there's a trunc?)
}
int16_t test_vaddv_s16(int16x4_t a1) {
// CHECK: test_vaddv_s16
return vaddv_s16(a1);
// CHECK: llvm.arm64.neon.saddv.i32.v4i16
// CHECK: llvm.aarch64.neon.saddv.i32.v4i16
// don't check for return here (there's a trunc?)
}
int32_t test_vaddv_s32(int32x2_t a1) {
// CHECK: test_vaddv_s32
return vaddv_s32(a1);
// CHECK: llvm.arm64.neon.saddv.i32.v2i32
// CHECK: llvm.aarch64.neon.saddv.i32.v2i32
// CHECK-NEXT: ret
}
uint8_t test_vaddv_u8(int8x8_t a1) {
// CHECK: test_vaddv_u8
return vaddv_u8(a1);
// CHECK: llvm.arm64.neon.uaddv.i32.v8i8
// CHECK: llvm.aarch64.neon.uaddv.i32.v8i8
// don't check for return here (there's a trunc?)
}
uint16_t test_vaddv_u16(int16x4_t a1) {
// CHECK: test_vaddv_u16
return vaddv_u16(a1);
// CHECK: llvm.arm64.neon.uaddv.i32.v4i16
// CHECK: llvm.aarch64.neon.uaddv.i32.v4i16
// don't check for return here (there's a trunc?)
}
uint32_t test_vaddv_u32(int32x2_t a1) {
// CHECK: test_vaddv_u32
return vaddv_u32(a1);
// CHECK: llvm.arm64.neon.uaddv.i32.v2i32
// CHECK: llvm.aarch64.neon.uaddv.i32.v2i32
// CHECK-NEXT: ret
}
int8_t test_vaddvq_s8(int8x16_t a1) {
// CHECK: test_vaddvq_s8
return vaddvq_s8(a1);
// CHECK: llvm.arm64.neon.saddv.i32.v16i8
// CHECK: llvm.aarch64.neon.saddv.i32.v16i8
// don't check for return here (there's a trunc?)
}
int16_t test_vaddvq_s16(int16x8_t a1) {
// CHECK: test_vaddvq_s16
return vaddvq_s16(a1);
// CHECK: llvm.arm64.neon.saddv.i32.v8i16
// CHECK: llvm.aarch64.neon.saddv.i32.v8i16
// don't check for return here (there's a trunc?)
}
int32_t test_vaddvq_s32(int32x4_t a1) {
// CHECK: test_vaddvq_s32
return vaddvq_s32(a1);
// CHECK: llvm.arm64.neon.saddv.i32.v4i32
// CHECK: llvm.aarch64.neon.saddv.i32.v4i32
// CHECK-NEXT: ret
}
uint8_t test_vaddvq_u8(int8x16_t a1) {
// CHECK: test_vaddvq_u8
return vaddvq_u8(a1);
// CHECK: llvm.arm64.neon.uaddv.i32.v16i8
// CHECK: llvm.aarch64.neon.uaddv.i32.v16i8
// don't check for return here (there's a trunc?)
}
uint16_t test_vaddvq_u16(int16x8_t a1) {
// CHECK: test_vaddvq_u16
return vaddvq_u16(a1);
// CHECK: llvm.arm64.neon.uaddv.i32.v8i16
// CHECK: llvm.aarch64.neon.uaddv.i32.v8i16
// don't check for return here (there's a trunc?)
}
uint32_t test_vaddvq_u32(int32x4_t a1) {
// CHECK: test_vaddvq_u32
return vaddvq_u32(a1);
// CHECK: llvm.arm64.neon.uaddv.i32.v4i32
// CHECK: llvm.aarch64.neon.uaddv.i32.v4i32
// CHECK-NEXT: ret
}

16
clang/test/CodeGen/arm64_vca.c
View File

@ -6,54 +6,54 @@
uint32x2_t test_vcale_f32(float32x2_t a1, float32x2_t a2) {
// CHECK: test_vcale_f32
return vcale_f32(a1, a2);
// CHECK: llvm.arm64.neon.facge.v2i32.v2f32
// CHECK: llvm.aarch64.neon.facge.v2i32.v2f32
// no check for ret here, as there is a bitcast
}
uint32x4_t test_vcaleq_f32(float32x4_t a1, float32x4_t a2) {
// CHECK: test_vcaleq_f32
return vcaleq_f32(a1, a2);
// CHECK: llvm.arm64.neon.facge.v4i32.v4f32{{.*a2,.*a1}}
// CHECK: llvm.aarch64.neon.facge.v4i32.v4f32{{.*a2,.*a1}}
// no check for ret here, as there is a bitcast
}
uint32x2_t test_vcalt_f32(float32x2_t a1, float32x2_t a2) {
// CHECK: test_vcalt_f32
return vcalt_f32(a1, a2);
// CHECK: llvm.arm64.neon.facgt.v2i32.v2f32{{.*a2,.*a1}}
// CHECK: llvm.aarch64.neon.facgt.v2i32.v2f32{{.*a2,.*a1}}
// no check for ret here, as there is a bitcast
}
uint32x4_t test_vcaltq_f32(float32x4_t a1, float32x4_t a2) {
// CHECK: test_vcaltq_f32
return vcaltq_f32(a1, a2);
// CHECK: llvm.arm64.neon.facgt.v4i32.v4f32{{.*a2,.*a1}}
// CHECK: llvm.aarch64.neon.facgt.v4i32.v4f32{{.*a2,.*a1}}
}
uint64x2_t test_vcagtq_f64(float64x2_t a1, float64x2_t a2) {
// CHECK: test_vcagtq_f64
return vcagtq_f64(a1, a2);
// CHECK: llvm.arm64.neon.facgt.v2i64.v2f64{{.*a1,.*a2}}
// CHECK: llvm.aarch64.neon.facgt.v2i64.v2f64{{.*a1,.*a2}}
// no check for ret here, as there is a bitcast
}
uint64x2_t test_vcaltq_f64(float64x2_t a1, float64x2_t a2) {
// CHECK: test_vcaltq_f64
return vcaltq_f64(a1, a2);
// CHECK: llvm.arm64.neon.facgt.v2i64.v2f64{{.*a2,.*a1}}
// CHECK: llvm.aarch64.neon.facgt.v2i64.v2f64{{.*a2,.*a1}}
// no check for ret here, as there is a bitcast
}
uint64x2_t test_vcageq_f64(float64x2_t a1, float64x2_t a2) {
// CHECK: test_vcageq_f64
return vcageq_f64(a1, a2);
// CHECK: llvm.arm64.neon.facge.v2i64.v2f64{{.*a1,.*a2}}
// CHECK: llvm.aarch64.neon.facge.v2i64.v2f64{{.*a1,.*a2}}
// no check for ret here, as there is a bitcast
}
uint64x2_t test_vcaleq_f64(float64x2_t a1, float64x2_t a2) {
// CHECK: test_vcaleq_f64
return vcaleq_f64(a1, a2);
// CHECK: llvm.arm64.neon.facge.v2i64.v2f64{{.*a2,.*a1}}
// CHECK: llvm.aarch64.neon.facge.v2i64.v2f64{{.*a2,.*a1}}
// no check for ret here, as there is a bitcast
}

2
clang/test/CodeGen/arm64_vcreate.c
View File

@ -17,7 +17,7 @@ float32x2_t test_vcreate_f32(uint64_t a1) {
float64x1_t test_vcreate_f64(uint64_t a1) {
// CHECK@ test_vcreate_f64
return vcreate_f64(a1);
// CHECK@ llvm.arm64.neon.saddlv.i64.v2i32
// CHECK@ llvm.aarch64.neon.saddlv.i64.v2i32
// CHECK-NEXT@ ret
}
*/

4
clang/test/CodeGen/arm64_vcvtfp.c
View File

@ -35,14 +35,14 @@ float32x4_t test_vcvt_high_f32_f64(float32x2_t x, float64x2_t v) {
float32x2_t test_vcvtx_f32_f64(float64x2_t v) {
// CHECK: test_vcvtx_f32_f64
return vcvtx_f32_f64(v);
// CHECK: llvm.arm64.neon.fcvtxn.v2f32.v2f64
// CHECK: llvm.aarch64.neon.fcvtxn.v2f32.v2f64
// CHECK-NEXT: ret
}
float32x4_t test_vcvtx_high_f32_f64(float32x2_t x, float64x2_t v) {
// CHECK: test_vcvtx_high_f32_f64
return vcvtx_high_f32_f64(x, v);
// CHECK: llvm.arm64.neon.fcvtxn.v2f32.v2f64
// CHECK: llvm.aarch64.neon.fcvtxn.v2f32.v2f64
// CHECK: shufflevector
// CHECK-NEXT: ret
}

2
clang/test/CodeGen/arm64_vneg.c
View File

@ -13,6 +13,6 @@ int64x2_t test_vnegq_s64(int64x2_t a1) {
int64x2_t test_vqnegq_s64(int64x2_t a1) {
// CHECK: test_vqnegq_s64
return vqnegq_s64(a1);
// CHECK: llvm.arm64.neon.sqneg.v2i64
// CHECK: llvm.aarch64.neon.sqneg.v2i64
// CHECK-NEXT: ret
}

2
clang/test/CodeGen/arm64_vset_lane.c
View File

@ -20,7 +20,7 @@ float16x8_t test_vsetq_lane_f16(float16_t *a1, float16x8_t a2) {
float64x1_t test_vset_lane_f64(float64_t a1, float64x1_t a2) {
// CHECK-LABEL@ test_vset_lane_f64
return vset_lane_f64(a1, a2, 0);
// CHECK@ @llvm.arm64.neon.smaxv.i32.v8i8
// CHECK@ @llvm.aarch64.neon.smaxv.i32.v8i8
}
#endif

112
clang/test/CodeGen/arm64_vshift.c
View File

@ -3,355 +3,355 @@
int8x8_t test_vqshl_n_s8(int8x8_t in) {
// CHECK-LABEL: @test_vqshl_n_s8
// CHECK: call <8 x i8> @llvm.arm64.neon.sqshl.v8i8(<8 x i8> %in, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
// CHECK: call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> %in, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
return vqshl_n_s8(in, 1);
}
int16x4_t test_vqshl_n_s16(int16x4_t in) {
// CHECK-LABEL: @test_vqshl_n_s16
// CHECK: call <4 x i16> @llvm.arm64.neon.sqshl.v4i16(<4 x i16> %in, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
// CHECK: call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> %in, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
return vqshl_n_s16(in, 1);
}
int32x2_t test_vqshl_n_s32(int32x2_t in) {
// CHECK-LABEL: @test_vqshl_n_s32
// CHECK: call <2 x i32> @llvm.arm64.neon.sqshl.v2i32(<2 x i32> %in, <2 x i32> <i32 1, i32 1>)
// CHECK: call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> %in, <2 x i32> <i32 1, i32 1>)
return vqshl_n_s32(in, 1);
}
int64x1_t test_vqshl_n_s64(int64x1_t in) {
// CHECK-LABEL: @test_vqshl_n_s64
// CHECK: call <1 x i64> @llvm.arm64.neon.sqshl.v1i64(<1 x i64> %in, <1 x i64> <i64 1>)
// CHECK: call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> %in, <1 x i64> <i64 1>)
return vqshl_n_s64(in, 1);
}
int8x16_t test_vqshlq_n_s8(int8x16_t in) {
// CHECK-LABEL: @test_vqshlq_n_s8
// CHECK: call <16 x i8> @llvm.arm64.neon.sqshl.v16i8(<16 x i8> %in, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
// CHECK: call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> %in, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
return vqshlq_n_s8(in, 1);
}
int16x8_t test_vqshlq_n_s16(int16x8_t in) {
// CHECK-LABEL: @test_vqshlq_n_s16
// CHECK: call <8 x i16> @llvm.arm64.neon.sqshl.v8i16(<8 x i16> %in, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
// CHECK: call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> %in, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
return vqshlq_n_s16(in, 1);
}
int32x4_t test_vqshlq_n_s32(int32x4_t in) {
// CHECK-LABEL: @test_vqshlq_n_s32
// CHECK: call <4 x i32> @llvm.arm64.neon.sqshl.v4i32(<4 x i32> %in, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
// CHECK: call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> %in, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
return vqshlq_n_s32(in, 1);
}
int64x2_t test_vqshlq_n_s64(int64x2_t in) {
// CHECK-LABEL: @test_vqshlq_n_s64
// CHECK: call <2 x i64> @llvm.arm64.neon.sqshl.v2i64(<2 x i64> %in, <2 x i64> <i64 1, i64 1>
// CHECK: call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> %in, <2 x i64> <i64 1, i64 1>
return vqshlq_n_s64(in, 1);
}
uint8x8_t test_vqshl_n_u8(uint8x8_t in) {
// CHECK-LABEL: @test_vqshl_n_u8
// CHECK: call <8 x i8> @llvm.arm64.neon.uqshl.v8i8(<8 x i8> %in, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
// CHECK: call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> %in, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
return vqshl_n_u8(in, 1);
}
uint16x4_t test_vqshl_n_u16(uint16x4_t in) {
// CHECK-LABEL: @test_vqshl_n_u16
// CHECK: call <4 x i16> @llvm.arm64.neon.uqshl.v4i16(<4 x i16> %in, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
// CHECK: call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> %in, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
return vqshl_n_u16(in, 1);
}
uint32x2_t test_vqshl_n_u32(uint32x2_t in) {
// CHECK-LABEL: @test_vqshl_n_u32
// CHECK: call <2 x i32> @llvm.arm64.neon.uqshl.v2i32(<2 x i32> %in, <2 x i32> <i32 1, i32 1>)
// CHECK: call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> %in, <2 x i32> <i32 1, i32 1>)
return vqshl_n_u32(in, 1);
}
uint64x1_t test_vqshl_n_u64(uint64x1_t in) {
// CHECK-LABEL: @test_vqshl_n_u64
// CHECK: call <1 x i64> @llvm.arm64.neon.uqshl.v1i64(<1 x i64> %in, <1 x i64> <i64 1>)
// CHECK: call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> %in, <1 x i64> <i64 1>)
return vqshl_n_u64(in, 1);
}
uint8x16_t test_vqshlq_n_u8(uint8x16_t in) {
// CHECK-LABEL: @test_vqshlq_n_u8
// CHECK: call <16 x i8> @llvm.arm64.neon.uqshl.v16i8(<16 x i8> %in, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
// CHECK: call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> %in, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
return vqshlq_n_u8(in, 1);
}
uint16x8_t test_vqshlq_n_u16(uint16x8_t in) {
// CHECK-LABEL: @test_vqshlq_n_u16
// CHECK: call <8 x i16> @llvm.arm64.neon.uqshl.v8i16(<8 x i16> %in, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
// CHECK: call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> %in, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
return vqshlq_n_u16(in, 1);
}
uint32x4_t test_vqshlq_n_u32(uint32x4_t in) {
// CHECK-LABEL: @test_vqshlq_n_u32
// CHECK: call <4 x i32> @llvm.arm64.neon.uqshl.v4i32(<4 x i32> %in, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
// CHECK: call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> %in, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
return vqshlq_n_u32(in, 1);
}
uint64x2_t test_vqshlq_n_u64(uint64x2_t in) {
// CHECK-LABEL: @test_vqshlq_n_u64
// CHECK: call <2 x i64> @llvm.arm64.neon.uqshl.v2i64(<2 x i64> %in, <2 x i64> <i64 1, i64 1>
// CHECK: call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> %in, <2 x i64> <i64 1, i64 1>
return vqshlq_n_u64(in, 1);
}
int8x8_t test_vrshr_n_s8(int8x8_t in) {
// CHECK-LABEL: @test_vrshr_n_s8
// CHECK: call <8 x i8> @llvm.arm64.neon.srshl.v8i8(<8 x i8> %in, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
// CHECK: call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> %in, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
return vrshr_n_s8(in, 1);
}
int16x4_t test_vrshr_n_s16(int16x4_t in) {
// CHECK-LABEL: @test_vrshr_n_s16
// CHECK: call <4 x i16> @llvm.arm64.neon.srshl.v4i16(<4 x i16> %in, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
// CHECK: call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> %in, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
return vrshr_n_s16(in, 1);
}
int32x2_t test_vrshr_n_s32(int32x2_t in) {
// CHECK-LABEL: @test_vrshr_n_s32
// CHECK: call <2 x i32> @llvm.arm64.neon.srshl.v2i32(<2 x i32> %in, <2 x i32> <i32 -1, i32 -1>)
// CHECK: call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> %in, <2 x i32> <i32 -1, i32 -1>)
return vrshr_n_s32(in, 1);
}
int64x1_t test_vrshr_n_s64(int64x1_t in) {
// CHECK-LABEL: @test_vrshr_n_s64
// CHECK: call <1 x i64> @llvm.arm64.neon.srshl.v1i64(<1 x i64> %in, <1 x i64> <i64 -1>)
// CHECK: call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> %in, <1 x i64> <i64 -1>)
return vrshr_n_s64(in, 1);
}
int8x16_t test_vrshrq_n_s8(int8x16_t in) {
// CHECK-LABEL: @test_vrshrq_n_s8
// CHECK: call <16 x i8> @llvm.arm64.neon.srshl.v16i8(<16 x i8> %in, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
// CHECK: call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> %in, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
return vrshrq_n_s8(in, 1);
}
int16x8_t test_vrshrq_n_s16(int16x8_t in) {
// CHECK-LABEL: @test_vrshrq_n_s16
// CHECK: call <8 x i16> @llvm.arm64.neon.srshl.v8i16(<8 x i16> %in, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
// CHECK: call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %in, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
return vrshrq_n_s16(in, 1);
}
int32x4_t test_vrshrq_n_s32(int32x4_t in) {
// CHECK-LABEL: @test_vrshrq_n_s32
// CHECK: call <4 x i32> @llvm.arm64.neon.srshl.v4i32(<4 x i32> %in, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
// CHECK: call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %in, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
return vrshrq_n_s32(in, 1);
}
int64x2_t test_vrshrq_n_s64(int64x2_t in) {
// CHECK-LABEL: @test_vrshrq_n_s64
// CHECK: call <2 x i64> @llvm.arm64.neon.srshl.v2i64(<2 x i64> %in, <2 x i64> <i64 -1, i64 -1>
// CHECK: call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %in, <2 x i64> <i64 -1, i64 -1>
return vrshrq_n_s64(in, 1);
}
uint8x8_t test_vrshr_n_u8(uint8x8_t in) {
// CHECK-LABEL: @test_vrshr_n_u8
// CHECK: call <8 x i8> @llvm.arm64.neon.urshl.v8i8(<8 x i8> %in, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
// CHECK: call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> %in, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
return vrshr_n_u8(in, 1);
}
uint16x4_t test_vrshr_n_u16(uint16x4_t in) {
// CHECK-LABEL: @test_vrshr_n_u16
// CHECK: call <4 x i16> @llvm.arm64.neon.urshl.v4i16(<4 x i16> %in, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
// CHECK: call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> %in, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
return vrshr_n_u16(in, 1);
}
uint32x2_t test_vrshr_n_u32(uint32x2_t in) {
// CHECK-LABEL: @test_vrshr_n_u32
// CHECK: call <2 x i32> @llvm.arm64.neon.urshl.v2i32(<2 x i32> %in, <2 x i32> <i32 -1, i32 -1>)
// CHECK: call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> %in, <2 x i32> <i32 -1, i32 -1>)
return vrshr_n_u32(in, 1);
}
uint64x1_t test_vrshr_n_u64(uint64x1_t in) {
// CHECK-LABEL: @test_vrshr_n_u64
// CHECK: call <1 x i64> @llvm.arm64.neon.urshl.v1i64(<1 x i64> %in, <1 x i64> <i64 -1>)
// CHECK: call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> %in, <1 x i64> <i64 -1>)
return vrshr_n_u64(in, 1);
}
uint8x16_t test_vrshrq_n_u8(uint8x16_t in) {
// CHECK-LABEL: @test_vrshrq_n_u8
// CHECK: call <16 x i8> @llvm.arm64.neon.urshl.v16i8(<16 x i8> %in, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
// CHECK: call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> %in, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
return vrshrq_n_u8(in, 1);
}
uint16x8_t test_vrshrq_n_u16(uint16x8_t in) {
// CHECK-LABEL: @test_vrshrq_n_u16
// CHECK: call <8 x i16> @llvm.arm64.neon.urshl.v8i16(<8 x i16> %in, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
// CHECK: call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %in, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
return vrshrq_n_u16(in, 1);
}
uint32x4_t test_vrshrq_n_u32(uint32x4_t in) {
// CHECK-LABEL: @test_vrshrq_n_u32
// CHECK: call <4 x i32> @llvm.arm64.neon.urshl.v4i32(<4 x i32> %in, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
// CHECK: call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %in, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
return vrshrq_n_u32(in, 1);
}
uint64x2_t test_vrshrq_n_u64(uint64x2_t in) {
// CHECK-LABEL: @test_vrshrq_n_u64
// CHECK: call <2 x i64> @llvm.arm64.neon.urshl.v2i64(<2 x i64> %in, <2 x i64> <i64 -1, i64 -1>
// CHECK: call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %in, <2 x i64> <i64 -1, i64 -1>
return vrshrq_n_u64(in, 1);
}
int8x8_t test_vqshlu_n_s8(int8x8_t in) {
// CHECK-LABEL: @test_vqshlu_n_s8
// CHECK: call <8 x i8> @llvm.arm64.neon.sqshlu.v8i8(<8 x i8> %in, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
// CHECK: call <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8> %in, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
return vqshlu_n_s8(in, 1);
}
int16x4_t test_vqshlu_n_s16(int16x4_t in) {
// CHECK-LABEL: @test_vqshlu_n_s16
// CHECK: call <4 x i16> @llvm.arm64.neon.sqshlu.v4i16(<4 x i16> %in, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
// CHECK: call <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16> %in, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
return vqshlu_n_s16(in, 1);
}
int32x2_t test_vqshlu_n_s32(int32x2_t in) {
// CHECK-LABEL: @test_vqshlu_n_s32
// CHECK: call <2 x i32> @llvm.arm64.neon.sqshlu.v2i32(<2 x i32> %in, <2 x i32> <i32 1, i32 1>)
// CHECK: call <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32> %in, <2 x i32> <i32 1, i32 1>)
return vqshlu_n_s32(in, 1);
}
int64x1_t test_vqshlu_n_s64(int64x1_t in) {
// CHECK-LABEL: @test_vqshlu_n_s64
// CHECK: call <1 x i64> @llvm.arm64.neon.sqshlu.v1i64(<1 x i64> %in, <1 x i64> <i64 1>)
// CHECK: call <1 x i64> @llvm.aarch64.neon.sqshlu.v1i64(<1 x i64> %in, <1 x i64> <i64 1>)
return vqshlu_n_s64(in, 1);
}
int8x16_t test_vqshluq_n_s8(int8x16_t in) {
// CHECK-LABEL: @test_vqshluq_n_s8
// CHECK: call <16 x i8> @llvm.arm64.neon.sqshlu.v16i8(<16 x i8> %in, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
// CHECK: call <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8> %in, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
return vqshluq_n_s8(in, 1);
}
int16x8_t test_vqshluq_n_s16(int16x8_t in) {
// CHECK-LABEL: @test_vqshluq_n_s16
// CHECK: call <8 x i16> @llvm.arm64.neon.sqshlu.v8i16(<8 x i16> %in, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
// CHECK: call <8 x i16> @llvm.aarch64.neon.sqshlu.v8i16(<8 x i16> %in, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
return vqshluq_n_s16(in, 1);
}
int32x4_t test_vqshluq_n_s32(int32x4_t in) {
// CHECK-LABEL: @test_vqshluq_n_s32
// CHECK: call <4 x i32> @llvm.arm64.neon.sqshlu.v4i32(<4 x i32> %in, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
// CHECK: call <4 x i32> @llvm.aarch64.neon.sqshlu.v4i32(<4 x i32> %in, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
return vqshluq_n_s32(in, 1);
}
int64x2_t test_vqshluq_n_s64(int64x2_t in) {
// CHECK-LABEL: @test_vqshluq_n_s64
// CHECK: call <2 x i64> @llvm.arm64.neon.sqshlu.v2i64(<2 x i64> %in, <2 x i64> <i64 1, i64 1>
// CHECK: call <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64> %in, <2 x i64> <i64 1, i64 1>
return vqshluq_n_s64(in, 1);
}
int8x8_t test_vrsra_n_s8(int8x8_t acc, int8x8_t in) {
// CHECK-LABEL: @test_vrsra_n_s8
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <8 x i8> @llvm.arm64.neon.srshl.v8i8(<8 x i8> %in, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> %in, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
// CHECK: add <8 x i8> [[TMP]], %acc
return vrsra_n_s8(acc, in, 1);
}
int16x4_t test_vrsra_n_s16(int16x4_t acc, int16x4_t in) {
// CHECK-LABEL: @test_vrsra_n_s16
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <4 x i16> @llvm.arm64.neon.srshl.v4i16(<4 x i16> %in, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> %in, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
// CHECK: add <4 x i16> [[TMP]], %acc
return vrsra_n_s16(acc, in, 1);
}
int32x2_t test_vrsra_n_s32(int32x2_t acc, int32x2_t in) {
// CHECK-LABEL: @test_vrsra_n_s32
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <2 x i32> @llvm.arm64.neon.srshl.v2i32(<2 x i32> %in, <2 x i32> <i32 -1, i32 -1>)
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> %in, <2 x i32> <i32 -1, i32 -1>)
// CHECK: add <2 x i32> [[TMP]], %acc
return vrsra_n_s32(acc, in, 1);
}
int64x1_t test_vrsra_n_s64(int64x1_t acc, int64x1_t in) {
// CHECK-LABEL: @test_vrsra_n_s64
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <1 x i64> @llvm.arm64.neon.srshl.v1i64(<1 x i64> %in, <1 x i64> <i64 -1>)
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> %in, <1 x i64> <i64 -1>)
// CHECK: add <1 x i64> [[TMP]], %acc
return vrsra_n_s64(acc, in, 1);
}
int8x16_t test_vrsraq_n_s8(int8x16_t acc, int8x16_t in) {
// CHECK-LABEL: @test_vrsraq_n_s8
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <16 x i8> @llvm.arm64.neon.srshl.v16i8(<16 x i8> %in, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> %in, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
// CHECK: add <16 x i8> [[TMP]], %acc
return vrsraq_n_s8(acc, in, 1);
}
int16x8_t test_vrsraq_n_s16(int16x8_t acc, int16x8_t in) {
// CHECK-LABEL: @test_vrsraq_n_s16
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <8 x i16> @llvm.arm64.neon.srshl.v8i16(<8 x i16> %in, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %in, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
// CHECK: add <8 x i16> [[TMP]], %acc
return vrsraq_n_s16(acc, in, 1);
}
int32x4_t test_vrsraq_n_s32(int32x4_t acc, int32x4_t in) {
// CHECK-LABEL: @test_vrsraq_n_s32
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <4 x i32> @llvm.arm64.neon.srshl.v4i32(<4 x i32> %in, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %in, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
// CHECK: add <4 x i32> [[TMP]], %acc
return vrsraq_n_s32(acc, in, 1);
}
int64x2_t test_vrsraq_n_s64(int64x2_t acc, int64x2_t in) {
// CHECK-LABEL: @test_vrsraq_n_s64
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <2 x i64> @llvm.arm64.neon.srshl.v2i64(<2 x i64> %in, <2 x i64> <i64 -1, i64 -1>)
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %in, <2 x i64> <i64 -1, i64 -1>)
// CHECK: add <2 x i64> [[TMP]], %acc
return vrsraq_n_s64(acc, in, 1);
}
uint8x8_t test_vrsra_n_u8(uint8x8_t acc, uint8x8_t in) {
// CHECK-LABEL: @test_vrsra_n_u8
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <8 x i8> @llvm.arm64.neon.urshl.v8i8(<8 x i8> %in, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> %in, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
// CHECK: add <8 x i8> [[TMP]], %acc
return vrsra_n_u8(acc, in, 1);
}
uint16x4_t test_vrsra_n_u16(uint16x4_t acc, uint16x4_t in) {
// CHECK-LABEL: @test_vrsra_n_u16
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <4 x i16> @llvm.arm64.neon.urshl.v4i16(<4 x i16> %in, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> %in, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
// CHECK: add <4 x i16> [[TMP]], %acc
return vrsra_n_u16(acc, in, 1);
}
uint32x2_t test_vrsra_n_u32(uint32x2_t acc, uint32x2_t in) {
// CHECK-LABEL: @test_vrsra_n_u32
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <2 x i32> @llvm.arm64.neon.urshl.v2i32(<2 x i32> %in, <2 x i32> <i32 -1, i32 -1>)
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> %in, <2 x i32> <i32 -1, i32 -1>)
// CHECK: add <2 x i32> [[TMP]], %acc
return vrsra_n_u32(acc, in, 1);
}
uint64x1_t test_vrsra_n_u64(uint64x1_t acc, uint64x1_t in) {
// CHECK-LABEL: @test_vrsra_n_u64
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <1 x i64> @llvm.arm64.neon.urshl.v1i64(<1 x i64> %in, <1 x i64> <i64 -1>)
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> %in, <1 x i64> <i64 -1>)
// CHECK: add <1 x i64> [[TMP]], %acc
return vrsra_n_u64(acc, in, 1);
}
uint8x16_t test_vrsraq_n_u8(uint8x16_t acc, uint8x16_t in) {
// CHECK-LABEL: @test_vrsraq_n_u8
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <16 x i8> @llvm.arm64.neon.urshl.v16i8(<16 x i8> %in, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> %in, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
// CHECK: add <16 x i8> [[TMP]], %acc
return vrsraq_n_u8(acc, in, 1);
}
uint16x8_t test_vrsraq_n_u16(uint16x8_t acc, uint16x8_t in) {
// CHECK-LABEL: @test_vrsraq_n_u16
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <8 x i16> @llvm.arm64.neon.urshl.v8i16(<8 x i16> %in, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %in, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
// CHECK: add <8 x i16> [[TMP]], %acc
return vrsraq_n_u16(acc, in, 1);
}
uint32x4_t test_vrsraq_n_u32(uint32x4_t acc, uint32x4_t in) {
// CHECK-LABEL: @test_vrsraq_n_u32
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <4 x i32> @llvm.arm64.neon.urshl.v4i32(<4 x i32> %in, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %in, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
// CHECK: add <4 x i32> [[TMP]], %acc
return vrsraq_n_u32(acc, in, 1);
}
uint64x2_t test_vrsraq_n_u64(uint64x2_t acc, uint64x2_t in) {
// CHECK-LABEL: @test_vrsraq_n_u64
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <2 x i64> @llvm.arm64.neon.urshl.v2i64(<2 x i64> %in, <2 x i64> <i64 -1, i64 -1>)
// CHECK: [[TMP:%[0-9a-zA-Z._]+]] = tail call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %in, <2 x i64> <i64 -1, i64 -1>)
// CHECK: add <2 x i64> [[TMP]], %acc
return vrsraq_n_u64(acc, in, 1);
}

40
clang/test/CodeGen/arm64_vsli.c
View File

@ -9,140 +9,140 @@
int8x8_t test_vsli_n_s8(int8x8_t a1, int8x8_t a2) {
// CHECK: test_vsli_n_s8
return vsli_n_s8(a1, a2, 3);
// CHECK: llvm.arm64.neon.vsli.v8i8
// CHECK: llvm.aarch64.neon.vsli.v8i8
// CHECK_CODEGEN: sli.8b v0, v1, #3
}
int16x4_t test_vsli_n_s16(int16x4_t a1, int16x4_t a2) {
// CHECK: test_vsli_n_s16
return vsli_n_s16(a1, a2, 3);
// CHECK: llvm.arm64.neon.vsli.v4i16
// CHECK: llvm.aarch64.neon.vsli.v4i16
// CHECK_CODEGEN: sli.4h v0, v1, #3
}
int32x2_t test_vsli_n_s32(int32x2_t a1, int32x2_t a2) {
// CHECK: test_vsli_n_s32
return vsli_n_s32(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsli.v2i32
// CHECK: llvm.aarch64.neon.vsli.v2i32
// CHECK_CODEGEN: sli.2s v0, v1, #1
}
int64x1_t test_vsli_n_s64(int64x1_t a1, int64x1_t a2) {
// CHECK: test_vsli_n_s64
return vsli_n_s64(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsli.v1i64
// CHECK: llvm.aarch64.neon.vsli.v1i64
// CHECK_CODEGEN: sli d0, d1, #1
}
uint8x8_t test_vsli_n_u8(uint8x8_t a1, uint8x8_t a2) {
// CHECK: test_vsli_n_u8
return vsli_n_u8(a1, a2, 3);
// CHECK: llvm.arm64.neon.vsli.v8i8
// CHECK: llvm.aarch64.neon.vsli.v8i8
// CHECK_CODEGEN: sli.8b v0, v1, #3
}
uint16x4_t test_vsli_n_u16(uint16x4_t a1, uint16x4_t a2) {
// CHECK: test_vsli_n_u16
return vsli_n_u16(a1, a2, 3);
// CHECK: llvm.arm64.neon.vsli.v4i16
// CHECK: llvm.aarch64.neon.vsli.v4i16
// CHECK_CODEGEN: sli.4h v0, v1, #3
}
uint32x2_t test_vsli_n_u32(uint32x2_t a1, uint32x2_t a2) {
// CHECK: test_vsli_n_u32
return vsli_n_u32(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsli.v2i32
// CHECK: llvm.aarch64.neon.vsli.v2i32
// CHECK_CODEGEN: sli.2s v0, v1, #1
}
uint64x1_t test_vsli_n_u64(uint64x1_t a1, uint64x1_t a2) {
// CHECK: test_vsli_n_u64
return vsli_n_u64(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsli.v1i64
// CHECK: llvm.aarch64.neon.vsli.v1i64
// CHECK_CODEGEN: sli d0, d1, #1
}
poly8x8_t test_vsli_n_p8(poly8x8_t a1, poly8x8_t a2) {
// CHECK: test_vsli_n_p8
return vsli_n_p8(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsli.v8i8
// CHECK: llvm.aarch64.neon.vsli.v8i8
// CHECK_CODEGEN: sli.8b v0, v1, #1
}
poly16x4_t test_vsli_n_p16(poly16x4_t a1, poly16x4_t a2) {
// CHECK: test_vsli_n_p16
return vsli_n_p16(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsli.v4i16
// CHECK: llvm.aarch64.neon.vsli.v4i16
// CHECK_CODEGEN: sli.4h v0, v1, #1
}
int8x16_t test_vsliq_n_s8(int8x16_t a1, int8x16_t a2) {
// CHECK: test_vsliq_n_s8
return vsliq_n_s8(a1, a2, 3);
// CHECK: llvm.arm64.neon.vsli.v16i8
// CHECK: llvm.aarch64.neon.vsli.v16i8
// CHECK_CODEGEN: sli.16b v0, v1, #3
}
int16x8_t test_vsliq_n_s16(int16x8_t a1, int16x8_t a2) {
// CHECK: test_vsliq_n_s16
return vsliq_n_s16(a1, a2, 3);
// CHECK: llvm.arm64.neon.vsli.v8i16
// CHECK: llvm.aarch64.neon.vsli.v8i16
// CHECK_CODEGEN: sli.8h v0, v1, #3
}
int32x4_t test_vsliq_n_s32(int32x4_t a1, int32x4_t a2) {
// CHECK: test_vsliq_n_s32
return vsliq_n_s32(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsli.v4i32
// CHECK: llvm.aarch64.neon.vsli.v4i32
// CHECK_CODEGEN: sli.4s v0, v1, #1
}
int64x2_t test_vsliq_n_s64(int64x2_t a1, int64x2_t a2) {
// CHECK: test_vsliq_n_s64
return vsliq_n_s64(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsli.v2i64
// CHECK: llvm.aarch64.neon.vsli.v2i64
// CHECK_CODEGEN: sli.2d v0, v1, #1
}
uint8x16_t test_vsliq_n_u8(uint8x16_t a1, uint8x16_t a2) {
// CHECK: test_vsliq_n_u8
return vsliq_n_u8(a1, a2, 3);
// CHECK: llvm.arm64.neon.vsli.v16i8
// CHECK: llvm.aarch64.neon.vsli.v16i8
// CHECK_CODEGEN: sli.16b v0, v1, #3
}
uint16x8_t test_vsliq_n_u16(uint16x8_t a1, uint16x8_t a2) {
// CHECK: test_vsliq_n_u16
return vsliq_n_u16(a1, a2, 3);
// CHECK: llvm.arm64.neon.vsli.v8i16
// CHECK: llvm.aarch64.neon.vsli.v8i16
// CHECK_CODEGEN: sli.8h v0, v1, #3
}
uint32x4_t test_vsliq_n_u32(uint32x4_t a1, uint32x4_t a2) {
// CHECK: test_vsliq_n_u32
return vsliq_n_u32(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsli.v4i32
// CHECK: llvm.aarch64.neon.vsli.v4i32
// CHECK_CODEGEN: sli.4s v0, v1, #1
}
uint64x2_t test_vsliq_n_u64(uint64x2_t a1, uint64x2_t a2) {
// CHECK: test_vsliq_n_u64
return vsliq_n_u64(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsli.v2i64
// CHECK: llvm.aarch64.neon.vsli.v2i64
// CHECK_CODEGEN: sli.2d v0, v1, #1
}
poly8x16_t test_vsliq_n_p8(poly8x16_t a1, poly8x16_t a2) {
// CHECK: test_vsliq_n_p8
return vsliq_n_p8(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsli.v16i8
// CHECK: llvm.aarch64.neon.vsli.v16i8
// CHECK_CODEGEN: sli.16b v0, v1, #1
}
poly16x8_t test_vsliq_n_p16(poly16x8_t a1, poly16x8_t a2) {
// CHECK: test_vsliq_n_p16
return vsliq_n_p16(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsli.v8i16
// CHECK: llvm.aarch64.neon.vsli.v8i16
// CHECK_CODEGEN: sli.8h v0, v1, #1
}

40
clang/test/CodeGen/arm64_vsri.c
View File

@ -10,140 +10,140 @@
int8x8_t test_vsri_n_s8(int8x8_t a1, int8x8_t a2) {
// CHECK: test_vsri_n_s8
return vsri_n_s8(a1, a2, 3);
// CHECK: llvm.arm64.neon.vsri.v8i8
// CHECK: llvm.aarch64.neon.vsri.v8i8
// CHECK_CODEGEN: sri.8b v0, v1, #3
}
int16x4_t test_vsri_n_s16(int16x4_t a1, int16x4_t a2) {
// CHECK: test_vsri_n_s16
return vsri_n_s16(a1, a2, 3);
// CHECK: llvm.arm64.neon.vsri.v4i16
// CHECK: llvm.aarch64.neon.vsri.v4i16
// CHECK_CODEGEN: sri.4h v0, v1, #3
}
int32x2_t test_vsri_n_s32(int32x2_t a1, int32x2_t a2) {
// CHECK: test_vsri_n_s32
return vsri_n_s32(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsri.v2i32
// CHECK: llvm.aarch64.neon.vsri.v2i32
// CHECK_CODEGEN: sri.2s v0, v1, #1
}
int64x1_t test_vsri_n_s64(int64x1_t a1, int64x1_t a2) {
// CHECK: test_vsri_n_s64
return vsri_n_s64(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsri.v1i64
// CHECK: llvm.aarch64.neon.vsri.v1i64
// CHECK_CODEGEN: sri d0, d1, #1
}
uint8x8_t test_vsri_n_u8(uint8x8_t a1, uint8x8_t a2) {
// CHECK: test_vsri_n_u8
return vsri_n_u8(a1, a2, 3);
// CHECK: llvm.arm64.neon.vsri.v8i8
// CHECK: llvm.aarch64.neon.vsri.v8i8
// CHECK_CODEGEN: sri.8b v0, v1, #3
}
uint16x4_t test_vsri_n_u16(uint16x4_t a1, uint16x4_t a2) {
// CHECK: test_vsri_n_u16
return vsri_n_u16(a1, a2, 3);
// CHECK: llvm.arm64.neon.vsri.v4i16
// CHECK: llvm.aarch64.neon.vsri.v4i16
// CHECK_CODEGEN: sri.4h v0, v1, #3
}
uint32x2_t test_vsri_n_u32(uint32x2_t a1, uint32x2_t a2) {
// CHECK: test_vsri_n_u32
return vsri_n_u32(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsri.v2i32
// CHECK: llvm.aarch64.neon.vsri.v2i32
// CHECK_CODEGEN: sri.2s v0, v1, #1
}
uint64x1_t test_vsri_n_u64(uint64x1_t a1, uint64x1_t a2) {
// CHECK: test_vsri_n_u64
return vsri_n_u64(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsri.v1i64
// CHECK: llvm.aarch64.neon.vsri.v1i64
// CHECK_CODEGEN: sri d0, d1, #1
}
poly8x8_t test_vsri_n_p8(poly8x8_t a1, poly8x8_t a2) {
// CHECK: test_vsri_n_p8
return vsri_n_p8(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsri.v8i8
// CHECK: llvm.aarch64.neon.vsri.v8i8
// CHECK_CODEGEN: sri.8b v0, v1, #1
}
poly16x4_t test_vsri_n_p16(poly16x4_t a1, poly16x4_t a2) {
// CHECK: test_vsri_n_p16
return vsri_n_p16(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsri.v4i16
// CHECK: llvm.aarch64.neon.vsri.v4i16
// CHECK_CODEGEN: sri.4h v0, v1, #1
}
int8x16_t test_vsriq_n_s8(int8x16_t a1, int8x16_t a2) {
// CHECK: test_vsriq_n_s8
return vsriq_n_s8(a1, a2, 3);
// CHECK: llvm.arm64.neon.vsri.v16i8
// CHECK: llvm.aarch64.neon.vsri.v16i8
// CHECK_CODEGEN: sri.16b v0, v1, #3
}
int16x8_t test_vsriq_n_s16(int16x8_t a1, int16x8_t a2) {
// CHECK: test_vsriq_n_s16
return vsriq_n_s16(a1, a2, 3);
// CHECK: llvm.arm64.neon.vsri.v8i16
// CHECK: llvm.aarch64.neon.vsri.v8i16
// CHECK_CODEGEN: sri.8h v0, v1, #3
}
int32x4_t test_vsriq_n_s32(int32x4_t a1, int32x4_t a2) {
// CHECK: test_vsriq_n_s32
return vsriq_n_s32(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsri.v4i32
// CHECK: llvm.aarch64.neon.vsri.v4i32
// CHECK_CODEGEN: sri.4s v0, v1, #1
}
int64x2_t test_vsriq_n_s64(int64x2_t a1, int64x2_t a2) {
// CHECK: test_vsriq_n_s64
return vsriq_n_s64(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsri.v2i64
// CHECK: llvm.aarch64.neon.vsri.v2i64
// CHECK_CODEGEN: sri.2d v0, v1, #1
}
uint8x16_t test_vsriq_n_u8(uint8x16_t a1, uint8x16_t a2) {
// CHECK: test_vsriq_n_u8
return vsriq_n_u8(a1, a2, 3);
// CHECK: llvm.arm64.neon.vsri.v16i8
// CHECK: llvm.aarch64.neon.vsri.v16i8
// CHECK_CODEGEN: sri.16b v0, v1, #3
}
uint16x8_t test_vsriq_n_u16(uint16x8_t a1, uint16x8_t a2) {
// CHECK: test_vsriq_n_u16
return vsriq_n_u16(a1, a2, 3);
// CHECK: llvm.arm64.neon.vsri.v8i16
// CHECK: llvm.aarch64.neon.vsri.v8i16
// CHECK_CODEGEN: sri.8h v0, v1, #3
}
uint32x4_t test_vsriq_n_u32(uint32x4_t a1, uint32x4_t a2) {
// CHECK: test_vsriq_n_u32
return vsriq_n_u32(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsri.v4i32
// CHECK: llvm.aarch64.neon.vsri.v4i32
// CHECK_CODEGEN: sri.4s v0, v1, #1
}
uint64x2_t test_vsriq_n_u64(uint64x2_t a1, uint64x2_t a2) {
// CHECK: test_vsriq_n_u64
return vsriq_n_u64(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsri.v2i64
// CHECK: llvm.aarch64.neon.vsri.v2i64
// CHECK_CODEGEN: sri.2d v0, v1, #1
}
poly8x16_t test_vsriq_n_p8(poly8x16_t a1, poly8x16_t a2) {
// CHECK: test_vsriq_n_p8
return vsriq_n_p8(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsri.v16i8
// CHECK: llvm.aarch64.neon.vsri.v16i8
// CHECK_CODEGEN: sri.16b v0, v1, #1
}
poly16x8_t test_vsriq_n_p16(poly16x8_t a1, poly16x8_t a2) {
// CHECK: test_vsriq_n_p16
return vsriq_n_p16(a1, a2, 1);
// CHECK: llvm.arm64.neon.vsri.v8i16
// CHECK: llvm.aarch64.neon.vsri.v8i16
// CHECK_CODEGEN: sri.8h v0, v1, #1
}

42
clang/test/CodeGen/builtins-arm-exclusive.c
View File

@ -21,10 +21,10 @@ int atomic_inc(int *addr) {
// CHECK: br i1 [[TST]], label {{%[a-zA-Z0-9.]+}}, label {{%[a-zA-Z0-9.]+}}
// CHECK-ARM64-LABEL: @atomic_inc
// CHECK-ARM64: [[OLDVAL:%.*]] = tail call i64 @llvm.arm64.ldxr.p0i32(i32* %addr)
// CHECK-ARM64: [[OLDVAL:%.*]] = tail call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
// CHECK-ARM64: [[INC:%.*]] = add i64 [[OLDVAL]], 1
// CHECK-ARM64: [[TRUNC:%.*]] = and i64 [[INC]], 4294967295
// CHECK-ARM64: [[FAILURE:%.*]] = tail call i32 @llvm.arm64.stxr.p0i32(i64 [[TRUNC]], i32* %addr)
// CHECK-ARM64: [[FAILURE:%.*]] = tail call i32 @llvm.aarch64.stxr.p0i32(i64 [[TRUNC]], i32* %addr)
// CHECK-ARM64: [[TST:%.*]] = icmp eq i32 [[FAILURE]], 0
// CHECK-ARM64: br i1 [[TST]], label {{%[a-zA-Z0-9.]+}}, label {{%[a-zA-Z0-9.]+}}
@ -40,7 +40,7 @@ int test_ldrex(char *addr, long long *addr64, float *addrfloat) {
// CHECK: [[INTRES:%.*]] = tail call i32 @llvm.arm.ldrex.p0i8(i8* %addr)
// CHECK: and i32 [[INTRES]], 255
// CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.arm64.ldxr.p0i8(i8* %addr)
// CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.aarch64.ldxr.p0i8(i8* %addr)
// CHECK-ARM64: [[TRUNCRES:%.*]] = trunc i64 [[INTRES]] to i32
// CHECK-ARM64: [[SEXTTMP:%.*]] = shl i32 [[TRUNCRES]], 24
// CHECK-ARM64: ashr exact i32 [[SEXTTMP]], 24
@ -52,7 +52,7 @@ int test_ldrex(char *addr, long long *addr64, float *addrfloat) {
// CHECK: ashr exact i32 [[TMPSEXT]], 16
// CHECK-ARM64: [[ADDR16:%.*]] = bitcast i8* %addr to i16*
// CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.arm64.ldxr.p0i16(i16* [[ADDR16]])
// CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.aarch64.ldxr.p0i16(i16* [[ADDR16]])
// CHECK-ARM64: [[TRUNCRES:%.*]] = trunc i64 [[INTRES]] to i32
// CHECK-ARM64: [[TMPSEXT:%.*]] = shl i32 [[TRUNCRES]], 16
// CHECK-ARM64: ashr exact i32 [[TMPSEXT]], 16
@ -62,20 +62,20 @@ int test_ldrex(char *addr, long long *addr64, float *addrfloat) {
// CHECK: call i32 @llvm.arm.ldrex.p0i32(i32* [[ADDR32]])
// CHECK-ARM64: [[ADDR32:%.*]] = bitcast i8* %addr to i32*
// CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.arm64.ldxr.p0i32(i32* [[ADDR32]])
// CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.aarch64.ldxr.p0i32(i32* [[ADDR32]])
// CHECK-ARM64: trunc i64 [[INTRES]] to i32
sum += __builtin_arm_ldrex((long long *)addr);
// CHECK: call { i32, i32 } @llvm.arm.ldrexd(i8* %addr)
// CHECK-ARM64: [[ADDR64:%.*]] = bitcast i8* %addr to i64*
// CHECK-ARM64: call i64 @llvm.arm64.ldxr.p0i64(i64* [[ADDR64]])
// CHECK-ARM64: call i64 @llvm.aarch64.ldxr.p0i64(i64* [[ADDR64]])
sum += __builtin_arm_ldrex(addr64);
// CHECK: [[ADDR64_AS8:%.*]] = bitcast i64* %addr64 to i8*
// CHECK: call { i32, i32 } @llvm.arm.ldrexd(i8* [[ADDR64_AS8]])
// CHECK-ARM64: call i64 @llvm.arm64.ldxr.p0i64(i64* %addr64)
// CHECK-ARM64: call i64 @llvm.aarch64.ldxr.p0i64(i64* %addr64)
sum += __builtin_arm_ldrex(addrfloat);
// CHECK: [[INTADDR:%.*]] = bitcast float* %addrfloat to i32*
@ -83,7 +83,7 @@ int test_ldrex(char *addr, long long *addr64, float *addrfloat) {
// CHECK: bitcast i32 [[INTRES]] to float
// CHECK-ARM64: [[INTADDR:%.*]] = bitcast float* %addrfloat to i32*
// CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.arm64.ldxr.p0i32(i32* [[INTADDR]])
// CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.aarch64.ldxr.p0i32(i32* [[INTADDR]])
// CHECK-ARM64: [[TRUNCRES:%.*]] = trunc i64 [[INTRES]] to i32
// CHECK-ARM64: bitcast i32 [[TRUNCRES]] to float
@ -97,21 +97,21 @@ int test_ldrex(char *addr, long long *addr64, float *addrfloat) {
// CHECK: [[INTRES:%.*]] = or i64 [[RESHIHI]], [[RESLO64]]
// CHECK: bitcast i64 [[INTRES]] to double
// CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.arm64.ldxr.p0i64(i64* [[ADDR64]])
// CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.aarch64.ldxr.p0i64(i64* [[ADDR64]])
// CHECK-ARM64: bitcast i64 [[INTRES]] to double
sum += *__builtin_arm_ldrex((int **)addr);
// CHECK: [[INTRES:%.*]] = tail call i32 @llvm.arm.ldrex.p0i32(i32* [[ADDR32]])
// CHECK: inttoptr i32 [[INTRES]] to i32*
// CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.arm64.ldxr.p0i64(i64* [[ADDR64]])
// CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.aarch64.ldxr.p0i64(i64* [[ADDR64]])
// CHECK-ARM64: inttoptr i64 [[INTRES]] to i32*
sum += __builtin_arm_ldrex((struct Simple **)addr)->a;
// CHECK: [[INTRES:%.*]] = tail call i32 @llvm.arm.ldrex.p0i32(i32* [[ADDR32]])
// CHECK: inttoptr i32 [[INTRES]] to %struct.Simple*
// CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.arm64.ldxr.p0i64(i64* [[ADDR64]])
// CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.aarch64.ldxr.p0i64(i64* [[ADDR64]])
// CHECK-ARM64: inttoptr i64 [[INTRES]] to %struct.Simple*
return sum;
}
@ -124,44 +124,44 @@ int test_strex(char *addr) {
res |= __builtin_arm_strex(4, addr);
// CHECK: call i32 @llvm.arm.strex.p0i8(i32 4, i8* %addr)
// CHECK-ARM64: call i32 @llvm.arm64.stxr.p0i8(i64 4, i8* %addr)
// CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i8(i64 4, i8* %addr)
res |= __builtin_arm_strex(42, (short *)addr);
// CHECK: [[ADDR16:%.*]] = bitcast i8* %addr to i16*
// CHECK: call i32 @llvm.arm.strex.p0i16(i32 42, i16* [[ADDR16]])
// CHECK-ARM64: [[ADDR16:%.*]] = bitcast i8* %addr to i16*
// CHECK-ARM64: call i32 @llvm.arm64.stxr.p0i16(i64 42, i16* [[ADDR16]])
// CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i16(i64 42, i16* [[ADDR16]])
res |= __builtin_arm_strex(42, (int *)addr);
// CHECK: [[ADDR32:%.*]] = bitcast i8* %addr to i32*
// CHECK: call i32 @llvm.arm.strex.p0i32(i32 42, i32* [[ADDR32]])
// CHECK-ARM64: [[ADDR32:%.*]] = bitcast i8* %addr to i32*
// CHECK-ARM64: call i32 @llvm.arm64.stxr.p0i32(i64 42, i32* [[ADDR32]])
// CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i32(i64 42, i32* [[ADDR32]])
res |= __builtin_arm_strex(42, (long long *)addr);
// CHECK: call i32 @llvm.arm.strexd(i32 42, i32 0, i8* %addr)
// CHECK-ARM64: [[ADDR64:%.*]] = bitcast i8* %addr to i64*
// CHECK-ARM64: call i32 @llvm.arm64.stxr.p0i64(i64 42, i64* [[ADDR64]])
// CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i64(i64 42, i64* [[ADDR64]])
res |= __builtin_arm_strex(2.71828f, (float *)addr);
// CHECK: call i32 @llvm.arm.strex.p0i32(i32 1076754509, i32* [[ADDR32]])
// CHECK-ARM64: call i32 @llvm.arm64.stxr.p0i32(i64 1076754509, i32* [[ADDR32]])
// CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i32(i64 1076754509, i32* [[ADDR32]])
res |= __builtin_arm_strex(3.14159, (double *)addr);
// CHECK: call i32 @llvm.arm.strexd(i32 -266631570, i32 1074340345, i8* %addr)
// CHECK-ARM64: call i32 @llvm.arm64.stxr.p0i64(i64 4614256650576692846, i64* [[ADDR64]])
// CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i64(i64 4614256650576692846, i64* [[ADDR64]])
res |= __builtin_arm_strex(&var, (struct Simple **)addr);
// CHECK: [[INTVAL:%.*]] = ptrtoint i16* %var to i32
// CHECK: call i32 @llvm.arm.strex.p0i32(i32 [[INTVAL]], i32* [[ADDR32]])
// CHECK-ARM64: [[INTVAL:%.*]] = ptrtoint i16* %var to i64
// CHECK-ARM64: call i32 @llvm.arm64.stxr.p0i64(i64 [[INTVAL]], i64* [[ADDR64]])
// CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i64(i64 [[INTVAL]], i64* [[ADDR64]])
return res;
}
@ -172,7 +172,7 @@ void test_clrex() {
__builtin_arm_clrex();
// CHECK: call void @llvm.arm.clrex()
// CHECK-ARM64: call void @llvm.arm64.clrex()
// CHECK-ARM64: call void @llvm.aarch64.clrex()
}
#ifdef __aarch64__
@ -183,7 +183,7 @@ __int128 test_ldrex_128(__int128 *addr) {
return __builtin_arm_ldrex(addr);
// CHECK-ARM64: [[ADDR8:%.*]] = bitcast i128* %addr to i8*
// CHECK-ARM64: [[STRUCTRES:%.*]] = tail call { i64, i64 } @llvm.arm64.ldxp(i8* [[ADDR8]])
// CHECK-ARM64: [[STRUCTRES:%.*]] = tail call { i64, i64 } @llvm.aarch64.ldxp(i8* [[ADDR8]])
// CHECK-ARM64: [[RESHI:%.*]] = extractvalue { i64, i64 } [[STRUCTRES]], 1
// CHECK-ARM64: [[RESLO:%.*]] = extractvalue { i64, i64 } [[STRUCTRES]], 0
// CHECK-ARM64: [[RESHI64:%.*]] = zext i64 [[RESHI]] to i128
@ -201,6 +201,6 @@ int test_strex_128(__int128 *addr, __int128 val) {
// CHECK-ARM64: [[VALHI128:%.*]] = lshr i128 %val, 64
// CHECK-ARM64: [[VALHI:%.*]] = trunc i128 [[VALHI128]] to i64
// CHECK-ARM64: [[ADDR8:%.*]] = bitcast i128* %addr to i8*
// CHECK-ARM64: [[RES:%.*]] = tail call i32 @llvm.arm64.stxp(i64 [[VALLO]], i64 [[VALHI]], i8* [[ADDR8]])
// CHECK-ARM64: [[RES:%.*]] = tail call i32 @llvm.aarch64.stxp(i64 [[VALLO]], i64 [[VALHI]], i8* [[ADDR8]])
}
#endif

28
clang/test/CodeGen/neon-crypto.c
View File

@ -14,83 +14,83 @@ uint8x16_t test_vaeseq_u8(uint8x16_t data, uint8x16_t key) {
// CHECK-LABEL: @test_vaeseq_u8
// CHECK-NO-CRYPTO: warning: implicit declaration of function 'vaeseq_u8' is invalid in C99
return vaeseq_u8(data, key);
// CHECK: call <16 x i8> @llvm.{{arm.neon|arm64.crypto}}.aese(<16 x i8> %data, <16 x i8> %key)
// CHECK: call <16 x i8> @llvm.{{arm.neon|aarch64.crypto}}.aese(<16 x i8> %data, <16 x i8> %key)
}
uint8x16_t test_vaesdq_u8(uint8x16_t data, uint8x16_t key) {
// CHECK-LABEL: @test_vaesdq_u8
return vaesdq_u8(data, key);
// CHECK: call <16 x i8> @llvm.{{arm.neon|arm64.crypto}}.aesd(<16 x i8> %data, <16 x i8> %key)
// CHECK: call <16 x i8> @llvm.{{arm.neon|aarch64.crypto}}.aesd(<16 x i8> %data, <16 x i8> %key)
}
uint8x16_t test_vaesmcq_u8(uint8x16_t data) {
// CHECK-LABEL: @test_vaesmcq_u8
return vaesmcq_u8(data);
// CHECK: call <16 x i8> @llvm.{{arm.neon|arm64.crypto}}.aesmc(<16 x i8> %data)
// CHECK: call <16 x i8> @llvm.{{arm.neon|aarch64.crypto}}.aesmc(<16 x i8> %data)
}
uint8x16_t test_vaesimcq_u8(uint8x16_t data) {
// CHECK-LABEL: @test_vaesimcq_u8
return vaesimcq_u8(data);
// CHECK: call <16 x i8> @llvm.{{arm.neon|arm64.crypto}}.aesimc(<16 x i8> %data)
// CHECK: call <16 x i8> @llvm.{{arm.neon|aarch64.crypto}}.aesimc(<16 x i8> %data)
}
uint32_t test_vsha1h_u32(uint32_t hash_e) {
// CHECK-LABEL: @test_vsha1h_u32
return vsha1h_u32(hash_e);
// CHECK: call i32 @llvm.{{arm.neon|arm64.crypto}}.sha1h(i32 %hash_e)
// CHECK: call i32 @llvm.{{arm.neon|aarch64.crypto}}.sha1h(i32 %hash_e)
}
uint32x4_t test_vsha1su1q_u32(uint32x4_t w0_3, uint32x4_t w12_15) {
// CHECK-LABEL: @test_vsha1su1q_u32
return vsha1su1q_u32(w0_3, w12_15);
// CHECK: call <4 x i32> @llvm.{{arm.neon|arm64.crypto}}.sha1su1(<4 x i32> %w0_3, <4 x i32> %w12_15)
// CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1su1(<4 x i32> %w0_3, <4 x i32> %w12_15)
}
uint32x4_t test_vsha256su0q_u32(uint32x4_t w0_3, uint32x4_t w4_7) {
// CHECK-LABEL: @test_vsha256su0q_u32
return vsha256su0q_u32(w0_3, w4_7);
// CHECK: call <4 x i32> @llvm.{{arm.neon|arm64.crypto}}.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7)
// CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7)
}
uint32x4_t test_vsha1cq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk) {
// CHECK-LABEL: @test_vsha1cq_u32
return vsha1cq_u32(hash_abcd, hash_e, wk);
// CHECK: call <4 x i32> @llvm.{{arm.neon|arm64.crypto}}.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
// CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
}
uint32x4_t test_vsha1pq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk) {
// CHECK-LABEL: @test_vsha1pq_u32
return vsha1pq_u32(hash_abcd, hash_e, wk);
// CHECK: call <4 x i32> @llvm.{{arm.neon|arm64.crypto}}.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
// CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
}
uint32x4_t test_vsha1mq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk) {
// CHECK-LABEL: @test_vsha1mq_u32
return vsha1mq_u32(hash_abcd, hash_e, wk);
// CHECK: call <4 x i32> @llvm.{{arm.neon|arm64.crypto}}.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
// CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
}
uint32x4_t test_vsha1su0q_u32(uint32x4_t w0_3, uint32x4_t w4_7, uint32x4_t w8_11) {
// CHECK-LABEL: @test_vsha1su0q_u32
return vsha1su0q_u32(w0_3, w4_7, w8_11);
// CHECK: call <4 x i32> @llvm.{{arm.neon|arm64.crypto}}.sha1su0(<4 x i32> %w0_3, <4 x i32> %w4_7, <4 x i32> %w8_11)
// CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1su0(<4 x i32> %w0_3, <4 x i32> %w4_7, <4 x i32> %w8_11)
}
uint32x4_t test_vsha256hq_u32(uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk) {
// CHECK-LABEL: @test_vsha256hq_u32
return vsha256hq_u32(hash_abcd, hash_efgh, wk);
// CHECK: call <4 x i32> @llvm.{{arm.neon|arm64.crypto}}.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
// CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
}
uint32x4_t test_vsha256h2q_u32(uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk) {
// CHECK-LABEL: @test_vsha256h2q_u32
return vsha256h2q_u32(hash_efgh, hash_abcd, wk);
// CHECK: call <4 x i32> @llvm.{{arm.neon|arm64.crypto}}.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
// CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
}
uint32x4_t test_vsha256su1q_u32(uint32x4_t w0_3, uint32x4_t w8_11, uint32x4_t w12_15) {
// CHECK-LABEL: @test_vsha256su1q_u32
return vsha256su1q_u32(w0_3, w8_11, w12_15);
// CHECK: call <4 x i32> @llvm.{{arm.neon|arm64.crypto}}.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
// CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
}

32
clang/test/Driver/arm-alignment.c
View File

@ -7,17 +7,17 @@
// RUN: %clang -target arm-none-gnueabi -mno-unaligned-access -munaligned-access -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-UNALIGNED-ARM < %t %s
// RUN: %clang -target arm64-none-gnueabi -munaligned-access -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-UNALIGNED-ARM64 < %t %s
// RUN: %clang -target aarch64-none-gnueabi -munaligned-access -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-UNALIGNED-AARCH64 < %t %s
// RUN: %clang -target arm64-none-gnueabi -mstrict-align -munaligned-access -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-UNALIGNED-ARM64 < %t %s
// RUN: %clang -target aarch64-none-gnueabi -mstrict-align -munaligned-access -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-UNALIGNED-AARCH64 < %t %s
// RUN: %clang -target arm64-none-gnueabi -mno-unaligned-access -munaligned-access -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-UNALIGNED-ARM64 < %t %s
// RUN: %clang -target aarch64-none-gnueabi -mno-unaligned-access -munaligned-access -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-UNALIGNED-AARCH64 < %t %s
// CHECK-UNALIGNED-ARM: "-backend-option" "-arm-no-strict-align"
// CHECK-UNALIGNED-ARM64: "-backend-option" "-arm64-no-strict-align"
// CHECK-UNALIGNED-AARCH64: "-backend-option" "-aarch64-no-strict-align"
// RUN: %clang -target arm-none-gnueabi -mno-unaligned-access -### %s 2> %t
@ -32,17 +32,17 @@
// RUN: %clang -target arm-none-gnueabi -munaligned-access -mstrict-align -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ALIGNED-ARM < %t %s
// RUN: %clang -target arm64-none-gnueabi -mno-unaligned-access -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ALIGNED-ARM64 < %t %s
// RUN: %clang -target aarch64-none-gnueabi -mno-unaligned-access -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ALIGNED-AARCH64 < %t %s
// RUN: %clang -target arm64-none-gnueabi -mstrict-align -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ALIGNED-ARM64 < %t %s
// RUN: %clang -target aarch64-none-gnueabi -mstrict-align -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ALIGNED-AARCH64 < %t %s
// RUN: %clang -target arm64-none-gnueabi -munaligned-access -mno-unaligned-access -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ALIGNED-ARM64 < %t %s
// RUN: %clang -target aarch64-none-gnueabi -munaligned-access -mno-unaligned-access -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ALIGNED-AARCH64 < %t %s
// RUN: %clang -target arm64-none-gnueabi -munaligned-access -mstrict-align -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ALIGNED-ARM64 < %t %s
// RUN: %clang -target aarch64-none-gnueabi -munaligned-access -mstrict-align -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ALIGNED-AARCH64 < %t %s
// CHECK-ALIGNED-ARM: "-backend-option" "-arm-strict-align"
// CHECK-ALIGNED-ARM64: "-backend-option" "-arm64-strict-align"
// CHECK-ALIGNED-AARCH64: "-backend-option" "-aarch64-strict-align"