From 5731fc75af70002359a684a553d83cc8c6cc61c2 Mon Sep 17 00:00:00 2001
From: Tim Northover <tnorthover@apple.com>
Date: Mon, 31 Mar 2014 15:46:34 +0000
Subject: [PATCH] ARM64: add more patterns for commuted fmsub operations.

llvm-svn: 205206
---
 llvm/lib/Target/ARM64/ARM64InstrInfo.td |  8 ++++++++
 llvm/test/CodeGen/ARM64/fmadd.ll        | 18 ++++++++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/llvm/lib/Target/ARM64/ARM64InstrInfo.td b/llvm/lib/Target/ARM64/ARM64InstrInfo.td
index 1b47fb576d29..8416fad9344f 100644
--- a/llvm/lib/Target/ARM64/ARM64InstrInfo.td
+++ b/llvm/lib/Target/ARM64/ARM64InstrInfo.td
@@ -1997,6 +1997,14 @@ defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
      TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
 
+// The following def pats catch the case where the LHS of an FMA is negated.
+// The TriOpFrag above catches the case where the middle operand is negated.
+def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Rd)),
+          (FMSUBSrrr FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
+
+def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Rd)),
+          (FMSUBDrrr FPR64:$Rd, FPR64:$Rn, FPR64:$Rm)>;
+
 //===----------------------------------------------------------------------===//
 // Floating point comparison instructions.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/ARM64/fmadd.ll b/llvm/test/CodeGen/ARM64/fmadd.ll
index 4ea841b8a132..d00aaef9c90d 100644
--- a/llvm/test/CodeGen/ARM64/fmadd.ll
+++ b/llvm/test/CodeGen/ARM64/fmadd.ll
@@ -26,6 +26,15 @@ entry:
   ret float %0
 }
 
+define float @fms32_com(float %a, float %b, float %c) nounwind readnone ssp {
+entry:
+; CHECK-LABEL: fms32_com:
+; CHECK: fmsub
+  %mul = fmul float %b, -1.000000e+00
+  %0 = tail call float @llvm.fma.f32(float %mul, float %a, float %c)
+  ret float %0
+}
+
 define float @fnms32(float %a, float %b, float %c) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: fnms32:
@@ -61,6 +70,15 @@ entry:
   ret double %0
 }
 
+define double @fms64_com(double %a, double %b, double %c) nounwind readnone ssp {
+; CHECK-LABEL: fms64_com:
+; CHECK: fmsub
+entry:
+  %mul = fmul double %b, -1.000000e+00
+  %0 = tail call double @llvm.fma.f64(double %mul, double %a, double %c)
+  ret double %0
+}
+
 define double @fnms64(double %a, double %b, double %c) nounwind readnone ssp {
 ; CHECK-LABEL: fnms64:
 ; CHECK: fnmsub