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ARM64: add more patterns for commuted fmsub operations. 

llvm-svn: 205206
This commit is contained in:
Tim Northover 2014-03-31 15:46:34 +00:00
parent 290e0698d4
commit 5731fc75af
2 changed files with 26 additions and 0 deletions
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8
llvm/lib/Target/ARM64/ARM64InstrInfo.td
View File

@ -1997,6 +1997,14 @@ defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
// The following def pats catch the case where the LHS of an FMA is negated.
// The TriOpFrag above catches the case where the middle operand is negated.
def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Rd)),
(FMSUBSrrr FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Rd)),
(FMSUBDrrr FPR64:$Rd, FPR64:$Rn, FPR64:$Rm)>;
//===----------------------------------------------------------------------===//
// Floating point comparison instructions.
//===----------------------------------------------------------------------===//

18
llvm/test/CodeGen/ARM64/fmadd.ll
View File

@ -26,6 +26,15 @@ entry:
ret float %0
}
define float @fms32_com(float %a, float %b, float %c) nounwind readnone ssp {
entry:
; CHECK-LABEL: fms32_com:
; CHECK: fmsub
%mul = fmul float %b, -1.000000e+00
%0 = tail call float @llvm.fma.f32(float %mul, float %a, float %c)
ret float %0
}
define float @fnms32(float %a, float %b, float %c) nounwind readnone ssp {
entry:
; CHECK-LABEL: fnms32:
@ -61,6 +70,15 @@ entry:
ret double %0
}
define double @fms64_com(double %a, double %b, double %c) nounwind readnone ssp {
; CHECK-LABEL: fms64_com:
; CHECK: fmsub
entry:
%mul = fmul double %b, -1.000000e+00
%0 = tail call double @llvm.fma.f64(double %mul, double %a, double %c)
ret double %0
}
define double @fnms64(double %a, double %b, double %c) nounwind readnone ssp {
; CHECK-LABEL: fnms64:
; CHECK: fnmsub