Allow PPC B and BLR to be if-converted into some predicated forms
This enables us to form predicated branches (which are the same conditional branches we had before) and also a larger set of predicated returns (including instructions like bdnzlr which is a conditional return and loop-counter decrement all in one). At the moment, if conversion does not capture all possible opportunities. A simple example is provided in early-ret2.ll, where if conversion forms one predicated return, and then the PPCEarlyReturn pass picks up the other one. So, at least for now, we'll keep both mechanisms. llvm-svn: 179134
This commit is contained in:
Hal Finkel
parent
aa577f464d
commit
5711eca19c
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@ -83,8 +83,17 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
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def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
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"bdnz $dst">;
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}
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let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
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def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
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"bdzlr", BrB, []>;
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def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
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"bdnzlr", BrB, []>;
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}
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}
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let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
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// Convenient aliases for call instructions
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let Uses = [RM] in {
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@ -876,6 +876,143 @@ bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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return true;
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}
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bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const {
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unsigned OpC = MI->getOpcode();
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switch (OpC) {
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default:
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return false;
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case PPC::BCC:
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case PPC::BCLR:
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case PPC::BDZLR:
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case PPC::BDZLR8:
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case PPC::BDNZLR:
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case PPC::BDNZLR8:
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return true;
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}
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}
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bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
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if (!MI->isTerminator())
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return false;
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// Conditional branch is a special case.
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if (MI->isBranch() && !MI->isBarrier())
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return true;
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return !isPredicated(MI);
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}
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bool PPCInstrInfo::PredicateInstruction(
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MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const {
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unsigned OpC = MI->getOpcode();
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if (OpC == PPC::BLR) {
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if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
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bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
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MI->setDesc(get(Pred[0].getImm() ?
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(isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) :
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(isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
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} else {
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MI->setDesc(get(PPC::BCLR));
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MachineInstrBuilder(*MI->getParent()->getParent(), MI)
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.addImm(Pred[0].getImm())
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.addReg(Pred[1].getReg());
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}
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return true;
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} else if (OpC == PPC::B) {
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if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
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bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
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MI->setDesc(get(Pred[0].getImm() ?
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(isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
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(isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
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} else {
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MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
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MI->RemoveOperand(0);
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MI->setDesc(get(PPC::BCC));
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MachineInstrBuilder(*MI->getParent()->getParent(), MI)
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.addImm(Pred[0].getImm())
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.addReg(Pred[1].getReg())
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.addMBB(MBB);
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}
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return true;
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}
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return false;
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}
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bool PPCInstrInfo::SubsumesPredicate(
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const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const {
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assert(Pred1.size() == 2 && "Invalid PPC first predicate");
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assert(Pred2.size() == 2 && "Invalid PPC second predicate");
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if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
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return false;
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if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
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return false;
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PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
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PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
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if (P1 == P2)
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return true;
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// Does P1 subsume P2, e.g. GE subsumes GT.
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if (P1 == PPC::PRED_LE &&
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(P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
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return true;
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if (P1 == PPC::PRED_GE &&
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(P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
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return true;
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return false;
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}
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bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const {
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// Note: At the present time, the contents of Pred from this function is
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// unused by IfConversion. This implementation follows ARM by pushing the
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// CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
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// predicate, instructions defining CTR or CTR8 are also included as
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// predicate-defining instructions.
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const TargetRegisterClass *RCs[] =
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{ &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
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&PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
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bool Found = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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for (int c = 0; c < 2 && !Found; ++c) {
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const TargetRegisterClass *RC = RCs[c];
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for (TargetRegisterClass::iterator I = RC->begin(),
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IE = RC->end(); I != IE; ++I) {
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if ((MO.isRegMask() && MO.clobbersPhysReg(*I)) ||
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(MO.isReg() && MO.isDef() && MO.getReg() == *I)) {
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Pred.push_back(MO);
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Found = true;
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}
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}
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}
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}
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return Found;
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}
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bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
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unsigned OpC = MI->getOpcode();
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switch (OpC) {
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default:
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return false;
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case PPC::B:
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case PPC::BLR:
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return true;
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}
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}
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/// GetInstSize - Return the number of bytes of code the specified
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/// instruction may be. This returns the maximum number of bytes.
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///
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@ -160,6 +160,53 @@ public:
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virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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unsigned Reg, MachineRegisterInfo *MRI) const;
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// If conversion by predication (only supported by some branch instructions).
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// All of the profitability checks always return true; it is always
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// profitable to use the predicated branches.
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virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
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unsigned NumCycles, unsigned ExtraPredCycles,
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const BranchProbability &Probability) const {
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return true;
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}
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virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumT, unsigned ExtraT,
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MachineBasicBlock &FMBB,
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unsigned NumF, unsigned ExtraF,
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const BranchProbability &Probability) const {
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return true;
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}
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virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
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unsigned NumCycles,
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const BranchProbability
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&Probability) const {
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return true;
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}
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virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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MachineBasicBlock &FMBB) const {
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return false;
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}
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// Predication support.
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bool isPredicated(const MachineInstr *MI) const;
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virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
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virtual
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bool PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const;
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virtual
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bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const;
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virtual bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const;
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virtual bool isPredicable(MachineInstr *MI) const;
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/// GetInstSize - Return the number of bytes of code the specified
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/// instruction may be. This returns the maximum number of bytes.
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///
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@ -518,6 +518,13 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
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let isReturn = 1, Uses = [LR, RM] in
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def BCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
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"b${cond:cc}lr ${cond:reg}", BrB, []>;
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let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
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def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
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"bdzlr", BrB, []>;
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def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
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"bdnzlr", BrB, []>;
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}
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}
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let Defs = [CTR], Uses = [CTR] in {
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@ -93,6 +93,7 @@ public:
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virtual bool addPreRegAlloc();
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virtual bool addILPOpts();
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virtual bool addInstSelector();
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virtual bool addPreSched2();
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virtual bool addPreEmitPass();
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};
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} // namespace
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@ -123,6 +124,13 @@ bool PPCPassConfig::addInstSelector() {
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return false;
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}
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bool PPCPassConfig::addPreSched2() {
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if (getOptLevel() != CodeGenOpt::None)
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addPass(&IfConverterID);
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return true;
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}
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bool PPCPassConfig::addPreEmitPass() {
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if (getOptLevel() != CodeGenOpt::None)
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addPass(createPPCEarlyReturnPass());
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@ -0,0 +1,63 @@
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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%struct.lua_TValue.17.692 = type { %union.Value.16.691, i32 }
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%union.Value.16.691 = type { %union.GCObject.15.690* }
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%union.GCObject.15.690 = type { %struct.lua_State.14.689 }
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%struct.lua_State.14.689 = type { %union.GCObject.15.690*, i8, i8, i8, %struct.lua_TValue.17.692*, %struct.lua_TValue.17.692*, %struct.global_State.10.685*, %struct.CallInfo.11.686*, i32*, %struct.lua_TValue.17.692*, %struct.lua_TValue.17.692*, %struct.CallInfo.11.686*, %struct.CallInfo.11.686*, i32, i32, i16, i16, i8, i8, i32, i32, void (%struct.lua_State.14.689*, %struct.lua_Debug.12.687*)*, %struct.lua_TValue.17.692, %struct.lua_TValue.17.692, %union.GCObject.15.690*, %union.GCObject.15.690*, %struct.lua_longjmp.13.688*, i64 }
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%struct.global_State.10.685 = type { %struct.stringtable.0.675, i8* (i8*, i8*, i64, i64)*, i8*, i8, i8, i32, %union.GCObject.15.690*, %union.GCObject.15.690**, %union.GCObject.15.690*, %union.GCObject.15.690*, %union.GCObject.15.690*, %union.GCObject.15.690*, %struct.Mbuffer.1.676, i64, i64, i64, i64, i32, i32, i32 (%struct.lua_State.14.689*)*, %struct.lua_TValue.17.692, %struct.lua_State.14.689*, %struct.UpVal.3.678, [9 x %struct.Table.7.682*], [17 x %union.TString.9.684*] }
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%struct.stringtable.0.675 = type { %union.GCObject.15.690**, i32, i32 }
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%struct.Mbuffer.1.676 = type { i8*, i64, i64 }
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%struct.UpVal.3.678 = type { %union.GCObject.15.690*, i8, i8, %struct.lua_TValue.17.692*, %union.anon.2.677 }
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%union.anon.2.677 = type { %struct.lua_TValue.17.692 }
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%struct.Table.7.682 = type { %union.GCObject.15.690*, i8, i8, i8, i8, %struct.Table.7.682*, %struct.lua_TValue.17.692*, %struct.Node.6.681*, %struct.Node.6.681*, %union.GCObject.15.690*, i32 }
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%struct.Node.6.681 = type { %struct.lua_TValue.17.692, %union.TKey.5.680 }
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%union.TKey.5.680 = type { %struct.anon.0.4.679 }
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%struct.anon.0.4.679 = type { %union.Value.16.691, i32, %struct.Node.6.681* }
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%union.TString.9.684 = type { %struct.anon.1.8.683 }
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%struct.anon.1.8.683 = type { %union.GCObject.15.690*, i8, i8, i8, i32, i64 }
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%struct.CallInfo.11.686 = type { %struct.lua_TValue.17.692*, %struct.lua_TValue.17.692*, %struct.lua_TValue.17.692*, i32*, i32, i32 }
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%struct.lua_Debug.12.687 = type { i32, i8*, i8*, i8*, i8*, i32, i32, i32, i32, [60 x i8], i32 }
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%struct.lua_longjmp.13.688 = type opaque
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define void @lua_xmove(i32 signext %n) #0 {
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entry:
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br i1 undef, label %for.end, label %if.end
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if.end: ; preds = %entry
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br i1 undef, label %for.body.lr.ph, label %for.end
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for.body.lr.ph: ; preds = %if.end
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br label %for.body
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for.body: ; preds = %for.body.for.body_crit_edge, %for.body.lr.ph
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%0 = phi %struct.lua_TValue.17.692* [ undef, %for.body.lr.ph ], [ %.pre, %for.body.for.body_crit_edge ]
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%indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body.for.body_crit_edge ]
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%tt = getelementptr inbounds %struct.lua_TValue.17.692* %0, i64 %indvars.iv, i32 1
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%1 = load i32* %tt, align 4, !tbaa !0
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store i32 %1, i32* undef, align 4, !tbaa !0
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%indvars.iv.next = add i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %for.end, label %for.body.for.body_crit_edge
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for.body.for.body_crit_edge: ; preds = %for.body
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%.pre = load %struct.lua_TValue.17.692** undef, align 8, !tbaa !3
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br label %for.body
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for.end: ; preds = %for.body, %if.end, %entry
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ret void
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; CHECK: @lua_xmove
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; CHECK: bnelr
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; CHECK: bnelr
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; CHECK: bdzlr
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}
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attributes #0 = { nounwind }
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!0 = metadata !{metadata !"int", metadata !1}
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!1 = metadata !{metadata !"omnipotent char", metadata !2}
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!2 = metadata !{metadata !"Simple C/C++ TBAA"}
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!3 = metadata !{metadata !"any pointer", metadata !1}
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@ -0,0 +1,26 @@
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define void @_Z8example3iPiS_() #0 {
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entry:
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br i1 undef, label %while.end, label %while.body.lr.ph
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while.body.lr.ph: ; preds = %entry
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br i1 undef, label %while.end, label %while.body
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while.body: ; preds = %while.body, %while.body.lr.ph
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br i1 false, label %while.end, label %while.body, !llvm.vectorizer.already_vectorized !0
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while.end: ; preds = %while.body, %while.body.lr.ph, %entry
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ret void
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; CHECK: @_Z8example3iPiS_
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; CHECK: bnelr
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; CHECK: bnelr
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}
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attributes #0 = { noinline nounwind }
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!0 = metadata !{}
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