[X86-64] Fix 256-bit SET0 lowering for non-VLX targets
If we don't have VLX then 256-bit SET0 should be lowered to VPXOR with ZMM registers. This restores functionality accidentally removed by r309926. Differential Revision: https://reviews.llvm.org/D62415 llvm-svn: 361843
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@ -3932,6 +3932,12 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
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MIB.addReg(SrcReg, RegState::ImplicitDefine);
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return true;
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}
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if (MI.getOpcode() == X86::AVX512_256_SET0) {
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// No VLX so we must reference a zmm.
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unsigned ZReg =
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TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
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MIB->getOperand(0).setReg(ZReg);
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}
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return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
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}
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case X86::V_SETALLONES:
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@ -0,0 +1,66 @@
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# Test that we emit VPXORD with ZMM registers instead of YMM
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# registers when we do not have VLX.
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#
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# RUN: llc -mtriple=x86_64-- -mattr=+avx512f -o - %s | FileCheck %s
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# CHECK: vpxord %zmm16, %zmm16, %zmm16
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--- |
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; ModuleID = 'test.ll'
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source_filename = "test.ll"
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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@tst_ = common global [4 x i64] zeroinitializer, align 64
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define void @main() #0 {
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bb0:
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%gep1 = bitcast [4 x i64]* @tst_ to [4 x i64]*
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%lsr.iv1 = bitcast [4 x i64]* %gep1 to <4 x i64>*
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store <4 x i64> zeroinitializer, <4 x i64>* %lsr.iv1, align 16
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ret void
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}
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attributes #0 = { "target-features"="+avx512f" }
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...
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---
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name: main
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins: []
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.bb0:
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renamable $ymm16 = AVX512_256_SET0
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VMOVAPSZmr $rip, 1, $noreg, @tst_, $noreg, killed renamable $zmm16 :: (store 32 into %ir.lsr.iv1, align 64)
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RET 0
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...
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