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Clarify debugging output. 

llvm-svn: 127771
This commit is contained in:
Jakob Stoklund Olesen 2011-03-16 22:56:08 +00:00
parent aaf5ddcf82
commit 557a82c099
3 changed files with 17 additions and 7 deletions
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4
llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -854,7 +854,7 @@ void LiveIntervals::shrinkToUses(LiveInterval *li,
assert(MI && "No instruction defining live value");
MI->addRegisterDead(li->reg, tri_);
if (dead && MI->allDefsAreDead()) {
DEBUG(dbgs() << "All defs dead: " << *MI);
DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
dead->push_back(MI);
}
}
@ -862,7 +862,7 @@ void LiveIntervals::shrinkToUses(LiveInterval *li,
// Move the trimmed ranges back.
li->ranges.swap(NewLI.ranges);
DEBUG(dbgs() << "Shrink: " << *li << '\n');
DEBUG(dbgs() << "Shrunk: " << *li << '\n');
}

10
llvm/lib/CodeGen/LiveRangeEdit.cpp
View File

@ -148,17 +148,21 @@ void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
while (!Dead.empty()) {
MachineInstr *MI = Dead.pop_back_val();
assert(MI->allDefsAreDead() && "Def isn't really dead");
SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
// Never delete inline asm.
if (MI->isInlineAsm())
if (MI->isInlineAsm()) {
DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
continue;
}
// Use the same criteria as DeadMachineInstructionElim.
bool SawStore = false;
if (!MI->isSafeToMove(&TII, 0, SawStore))
if (!MI->isSafeToMove(&TII, 0, SawStore)) {
DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
continue;
}
SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
// Check for live intervals that may shrink

10
llvm/lib/CodeGen/RegAllocGreedy.cpp
View File

@ -646,7 +646,9 @@ void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, unsigned PhysReg,
IndexPair &IP = InterferenceRanges[i];
DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " -> EB#"
<< Bundles->getBundle(BI.MBB->getNumber(), 1)
<< " intf [" << IP.first << ';' << IP.second << ')');
<< " [" << BI.Start << ';' << BI.LastSplitPoint << '-'
<< BI.Stop << ") intf [" << IP.first << ';' << IP.second
<< ')');
// The interference interval should either be invalid or overlap MBB.
assert((!IP.first.isValid() || IP.first < BI.Stop) && "Bad interference");
@ -741,7 +743,8 @@ void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, unsigned PhysReg,
IndexPair &IP = InterferenceRanges[i];
DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0)
<< " -> BB#" << BI.MBB->getNumber());
<< " -> BB#" << BI.MBB->getNumber() << " [" << BI.Start << ';'
<< BI.LastSplitPoint << '-' << BI.Stop << ')');
// Check interference entering the block.
if (!IP.first.isValid()) {
@ -1266,6 +1269,9 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
LiveRangeEdit LRE(VirtReg, NewVRegs, this);
spiller().spill(LRE);
if (VerifyEnabled)
MF->verify(this, "After spilling");
// The live virtual register requesting allocation was spilled, so tell
// the caller not to allocate anything during this round.
return 0;