Move the last piece of SSE2 convert instructions to the Convert Instructions section
llvm-svn: 106877
This commit is contained in:
Bruno Cardoso Lopes
parent
62d1403a03
commit
553fafc6ce
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@ -842,6 +842,157 @@ defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load /*dummy*/,
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SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
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}
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/// SSE 2 Only
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def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
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"cvtsd2ss\t{$src, $dst|$dst, $src}",
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[(set FR32:$dst, (fround FR64:$src))]>;
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def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
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"cvtsd2ss\t{$src, $dst|$dst, $src}",
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[(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
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Requires<[HasSSE2, OptForSize]>;
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def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}", []>;
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def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}", []>;
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// SSE2 instructions with XS prefix
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def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
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"cvtss2sd\t{$src, $dst|$dst, $src}",
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[(set FR64:$dst, (fextend FR32:$src))]>, XS,
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Requires<[HasSSE2]>;
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def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
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"cvtss2sd\t{$src, $dst|$dst, $src}",
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[(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
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Requires<[HasSSE2, OptForSize]>;
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def : Pat<(extloadf32 addr:$src),
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(CVTSS2SDrr (MOVSSrm addr:$src))>,
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Requires<[HasSSE2, OptForSpeed]>;
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// SSE2 instructions without OpSize prefix
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def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtdq2ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
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TB, Requires<[HasSSE2]>;
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def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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"cvtdq2ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2ps
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(bitconvert (memopv2i64 addr:$src))))]>,
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TB, Requires<[HasSSE2]>;
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// SSE2 instructions with XS prefix
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def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtdq2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
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XS, Requires<[HasSSE2]>;
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def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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"cvtdq2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2pd
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(bitconvert (memopv2i64 addr:$src))))]>,
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XS, Requires<[HasSSE2]>;
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def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
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def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2dq
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(memop addr:$src)))]>;
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// SSE2 packed instructions with XS prefix
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def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}", []>;
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def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}", []>;
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def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(int_x86_sse2_cvttps2dq VR128:$src))]>,
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XS, Requires<[HasSSE2]>;
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def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvttps2dq
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(memop addr:$src)))]>,
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XS, Requires<[HasSSE2]>;
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// SSE2 packed instructions with XD prefix
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def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtpd2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
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XD, Requires<[HasSSE2]>;
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def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtpd2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtpd2dq
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(memop addr:$src)))]>,
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XD, Requires<[HasSSE2]>;
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def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvttpd2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
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def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
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"cvttpd2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvttpd2dq
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(memop addr:$src)))]>;
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// SSE2 instructions without OpSize prefix
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def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
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def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
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"cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
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def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtps2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
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TB, Requires<[HasSSE2]>;
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def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
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"cvtps2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2pd
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(load addr:$src)))]>,
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TB, Requires<[HasSSE2]>;
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def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
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def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
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def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtpd2ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
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def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtpd2ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtpd2ps
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(memop addr:$src)))]>;
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// Match intrinsics which expect XMM operand(s).
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// Aliases for intrinsics
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let Constraints = "$src1 = $dst" in {
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def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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"cvtsd2ss\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
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VR128:$src2))]>;
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def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
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"cvtsd2ss\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
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(load addr:$src2)))]>;
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def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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"cvtss2sd\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
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VR128:$src2))]>, XS,
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Requires<[HasSSE2]>;
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def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
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"cvtss2sd\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
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(load addr:$src2)))]>, XS,
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Requires<[HasSSE2]>;
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}
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Compare Instructions
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//===----------------------------------------------------------------------===//
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@ -1611,156 +1762,6 @@ def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
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// SSE2 Instructions
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//===---------------------------------------------------------------------===//
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// Conversion instructions
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def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
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"cvtsd2ss\t{$src, $dst|$dst, $src}",
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[(set FR32:$dst, (fround FR64:$src))]>;
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def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
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"cvtsd2ss\t{$src, $dst|$dst, $src}",
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[(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
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Requires<[HasSSE2, OptForSize]>;
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def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}", []>;
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def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}", []>;
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// SSE2 instructions with XS prefix
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def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
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"cvtss2sd\t{$src, $dst|$dst, $src}",
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[(set FR64:$dst, (fextend FR32:$src))]>, XS,
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Requires<[HasSSE2]>;
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def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
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"cvtss2sd\t{$src, $dst|$dst, $src}",
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[(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
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Requires<[HasSSE2, OptForSize]>;
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def : Pat<(extloadf32 addr:$src),
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(CVTSS2SDrr (MOVSSrm addr:$src))>,
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Requires<[HasSSE2, OptForSpeed]>;
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// SSE2 instructions without OpSize prefix
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def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtdq2ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
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TB, Requires<[HasSSE2]>;
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def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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"cvtdq2ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2ps
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(bitconvert (memopv2i64 addr:$src))))]>,
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TB, Requires<[HasSSE2]>;
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// SSE2 instructions with XS prefix
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def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtdq2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
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XS, Requires<[HasSSE2]>;
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def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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"cvtdq2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2pd
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(bitconvert (memopv2i64 addr:$src))))]>,
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XS, Requires<[HasSSE2]>;
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def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
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def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2dq
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(memop addr:$src)))]>;
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// SSE2 packed instructions with XS prefix
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def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}", []>;
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def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}", []>;
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def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(int_x86_sse2_cvttps2dq VR128:$src))]>,
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XS, Requires<[HasSSE2]>;
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def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvttps2dq
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(memop addr:$src)))]>,
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XS, Requires<[HasSSE2]>;
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// SSE2 packed instructions with XD prefix
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def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtpd2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
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XD, Requires<[HasSSE2]>;
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def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtpd2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtpd2dq
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(memop addr:$src)))]>,
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XD, Requires<[HasSSE2]>;
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def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvttpd2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
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def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
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"cvttpd2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvttpd2dq
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(memop addr:$src)))]>;
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// SSE2 instructions without OpSize prefix
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def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
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def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
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"cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
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def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtps2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
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TB, Requires<[HasSSE2]>;
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def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
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"cvtps2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2pd
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(load addr:$src)))]>,
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TB, Requires<[HasSSE2]>;
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def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
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def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
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def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtpd2ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
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def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtpd2ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtpd2ps
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(memop addr:$src)))]>;
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// Match intrinsics which expect XMM operand(s).
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// Aliases for intrinsics
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let Constraints = "$src1 = $dst" in {
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def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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"cvtsd2ss\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
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VR128:$src2))]>;
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def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
|
||||
"cvtsd2ss\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
|
||||
(load addr:$src2)))]>;
|
||||
def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
|
||||
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
||||
"cvtss2sd\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
|
||||
VR128:$src2))]>, XS,
|
||||
Requires<[HasSSE2]>;
|
||||
def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
|
||||
"cvtss2sd\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
|
||||
(load addr:$src2)))]>, XS,
|
||||
Requires<[HasSSE2]>;
|
||||
}
|
||||
|
||||
// Arithmetic
|
||||
|
||||
/// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
|
||||
|
|
|
|||
Loading…
Reference in New Issue