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[SelectionDAG] Add scalarization of ABS node (PR41149) 

Patch by: @ikulagin (Ivan Kulagin)

Differential Revision: https://reviews.llvm.org/D59577

llvm-svn: 356656
This commit is contained in:
Simon Pilgrim 2019-03-21 11:18:54 +00:00
parent 045b8544fd
commit 54ed653870
2 changed files with 28 additions and 0 deletions
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1
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -68,6 +68,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
case ISD::ZERO_EXTEND_VECTOR_INREG:
R = ScalarizeVecRes_VecInregOp(N);
break;
case ISD::ABS:
case ISD::ANY_EXTEND:
case ISD::BITREVERSE:
case ISD::BSWAP:

27
llvm/test/CodeGen/WebAssembly/PR41149.ll Normal file
View File

@ -0,0 +1,27 @@
; RUN: llc < %s -mtriple=wasm32-unknown-unknown | FileCheck %s
; Regression test for PR41149.
define void @mod() {
; CHECK-LABEL: mod:
; CHECK-NEXT: .functype mod () -> ()
; CHECK: local.get 0
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.load8_s 0
; CHECK-NEXT: local.tee 0
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const 31
; CHECK-NEXT: i32.shr_s
; CHECK-NEXT: local.tee 0
; CHECK-NEXT: i32.add
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.xor
; CHECK-NEXT: i32.store8 0
%tmp = load <4 x i8>, <4 x i8>* undef
%tmp2 = icmp slt <4 x i8> %tmp, zeroinitializer
%tmp3 = sub <4 x i8> zeroinitializer, %tmp
%tmp4 = select <4 x i1> %tmp2, <4 x i8> %tmp3, <4 x i8> %tmp
store <4 x i8> %tmp4, <4 x i8>* undef
ret void
}