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AArch64: allow 64-bit access to sysregs. 

Although all the registers are actually 32-bits, I think we have to assume the
high 32-bits could be RES0 (the ARM ARM is unclear). If so, reading as a 32-bit
register can require extra zero extension operations.

llvm-svn: 266212
This commit is contained in:
Tim Northover 2016-04-13 17:08:55 +00:00
parent 99694feca5
commit 54e5000e2a
2 changed files with 3 additions and 3 deletions
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2
clang/lib/Sema/SemaChecking.cpp
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@ -1155,7 +1155,7 @@ bool Sema::CheckAArch64BuiltinFunctionCall(unsigned BuiltinID,
if (BuiltinID == AArch64::BI__builtin_arm_rsr64 ||
BuiltinID == AArch64::BI__builtin_arm_wsr64)
return SemaBuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5, false);
return SemaBuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5, true);
if (BuiltinID == AArch64::BI__builtin_arm_rsr ||
BuiltinID == AArch64::BI__builtin_arm_rsrp ||

4
clang/test/Sema/aarch64-special-register.c
View File

@ -13,7 +13,7 @@ void wsrp_1(void *v) {
}
void wsr64_1(unsigned long v) {
__builtin_arm_wsr64("sysreg", v); //expected-error {{invalid special register for builtin}}
__builtin_arm_wsr64("sysreg", v);
}
unsigned rsr_1() {
@ -25,7 +25,7 @@ void *rsrp_1() {
}
unsigned long rsr64_1() {
return __builtin_arm_rsr64("sysreg"); //expected-error {{invalid special register for builtin}}
return __builtin_arm_rsr64("sysreg");
}
void wsr_2(unsigned v) {