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Added isDef field to MachineOperand class - Ruchira 

llvm-svn: 349
This commit is contained in:
Ruchira Sasanka 2001-08-07 20:14:30 +00:00
parent 22db4f9b7c
commit 5303bac986
1 changed files with 18 additions and 7 deletions
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25
llvm/include/llvm/CodeGen/MachineInstr.h
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@ -85,6 +85,8 @@ private:
int64_t immedVal; // constant value for an explicit constant int64_t immedVal; // constant value for an explicit constant
}; };
public: public:
/*ctor*/ MachineOperand (); /*ctor*/ MachineOperand ();
/*ctor*/ MachineOperand (MachineOperandType operandType, /*ctor*/ MachineOperand (MachineOperandType operandType,
@ -111,6 +113,9 @@ public:
return immedVal; return immedVal;
} }
bool isDef; // is this a defition for the value
// made public for faster access
public: public:
friend ostream& operator<<(ostream& os, const MachineOperand& mop); friend ostream& operator<<(ostream& os, const MachineOperand& mop);
@ -134,7 +139,8 @@ MachineOperand::MachineOperand()
: opType(MO_VirtualRegister), : opType(MO_VirtualRegister),
value(NULL), value(NULL),
regNum(0), regNum(0),
immedVal(0) immedVal(0),
isDef(false)
{} {}
inline inline
@ -143,12 +149,14 @@ MachineOperand::MachineOperand(MachineOperandType operandType,
: opType(operandType), : opType(operandType),
value(_val), value(_val),
regNum(0), regNum(0),
immedVal(0) immedVal(0),
isDef(false)
{} {}
inline inline
MachineOperand::MachineOperand(const MachineOperand& mo) MachineOperand::MachineOperand(const MachineOperand& mo)
: opType(mo.opType) : opType(mo.opType),
isDef(false)
{ {
switch(opType) { switch(opType) {
case MO_VirtualRegister: case MO_VirtualRegister:
@ -240,12 +248,13 @@ public:
// Access to set the operands when building the machine instruction // Access to set the operands when building the machine instruction
void SetMachineOperand(unsigned int i, void SetMachineOperand(unsigned int i,
MachineOperand::MachineOperandType operandType, MachineOperand::MachineOperandType operandType,
Value* _val); Value* _val, bool isDef=false);
void SetMachineOperand(unsigned int i, void SetMachineOperand(unsigned int i,
MachineOperand::MachineOperandType operandType, MachineOperand::MachineOperandType operandType,
int64_t intValue); int64_t intValue, bool isDef=false);
void SetMachineOperand(unsigned int i, void SetMachineOperand(unsigned int i,
unsigned int regNum); unsigned int regNum,
bool isDef=false);
}; };
inline const MachineOpCode inline const MachineOpCode
@ -299,7 +308,9 @@ public:
inline _V* operator*() const { return minstr->getOperand(i).getVRegValue();} inline _V* operator*() const { return minstr->getOperand(i).getVRegValue();}
inline _V* operator->() const { return operator*(); } inline _V* operator->() const { return operator*(); }
inline bool isDef () const { return (((int) i) == resultPos); } // inline bool isDef () const { return (((int) i) == resultPos); }
inline bool isDef () const { return minstr->getOperand(i).isDef; }
inline bool done () const { return (i == minstr->getNumOperands()); } inline bool done () const { return (i == minstr->getNumOperands()); }
inline _Self& operator++() { i++; skipToNextVal(); return *this; } inline _Self& operator++() { i++; skipToNextVal(); return *this; }