Tidy up code moving patterns to their appropriate place!
llvm-svn: 139064
This commit is contained in:
Bruno Cardoso Lopes
parent
aad5e50ded
commit
521b0cfdc6
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@ -119,9 +119,11 @@ multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
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// Non-instruction patterns
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//===----------------------------------------------------------------------===//
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// A vector extract of the first f32 position is a subregister copy
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// A vector extract of the first f32/f64 position is a subregister copy
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def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
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(f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
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def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
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(f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
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// A 128-bit subvector extract from the first 256-bit vector position
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// is a subregister copy that needs no instruction.
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@ -236,6 +238,24 @@ let Predicates = [HasAVX] in {
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def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
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}
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// Alias instructions that map fld0 to pxor for sse.
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// FIXME: Set encoding to pseudo!
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let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
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canFoldAsLoad = 1 in {
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def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
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[(set FR32:$dst, fp32imm0)]>,
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Requires<[HasSSE1]>, TB, OpSize;
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def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
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[(set FR64:$dst, fpimm0)]>,
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Requires<[HasSSE2]>, TB, OpSize;
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def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
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[(set FR32:$dst, fp32imm0)]>,
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Requires<[HasAVX]>, TB, OpSize, VEX_4V;
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def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
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[(set FR64:$dst, fpimm0)]>,
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Requires<[HasAVX]>, TB, OpSize, VEX_4V;
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}
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//===----------------------------------------------------------------------===//
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// AVX & SSE - Zero/One Vectors
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//===----------------------------------------------------------------------===//
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@ -294,6 +314,21 @@ def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
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def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
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(SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
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// We set canFoldAsLoad because this can be converted to a constant-pool
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// load of an all-ones value if folding it would be beneficial.
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// FIXME: Change encoding to pseudo! This is blocked right now by the x86
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// JIT implementation, it does not expand the instructions below like
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// X86MCInstLower does.
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let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
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def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v4i32 immAllOnesV))]>;
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let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
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def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Move FP Scalar Instructions
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//
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@ -783,6 +818,38 @@ let Predicates = [HasAVX] in {
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(VMOVUPSYmr addr:$dst, VR256:$src)>;
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}
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// Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
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// bits are disregarded. FIXME: Set encoding to pseudo!
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let neverHasSideEffects = 1 in {
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def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
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"movaps\t{$src, $dst|$dst, $src}", []>;
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def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
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"movapd\t{$src, $dst|$dst, $src}", []>;
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def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
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"movaps\t{$src, $dst|$dst, $src}", []>, VEX;
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def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
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"movapd\t{$src, $dst|$dst, $src}", []>, VEX;
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}
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// Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
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// bits are disregarded. FIXME: Set encoding to pseudo!
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let canFoldAsLoad = 1, isReMaterializable = 1 in {
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def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
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"movaps\t{$src, $dst|$dst, $src}",
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[(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
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def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
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"movapd\t{$src, $dst|$dst, $src}",
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[(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
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let isCodeGenOnly = 1 in {
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def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
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"movaps\t{$src, $dst|$dst, $src}",
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[(set FR32:$dst, (alignedloadfsf32 addr:$src))]>, VEX;
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def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
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"movapd\t{$src, $dst|$dst, $src}",
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[(set FR64:$dst, (alignedloadfsf64 addr:$src))]>, VEX;
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}
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}
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Move Low packed FP Instructions
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//===----------------------------------------------------------------------===//
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@ -1480,6 +1547,13 @@ def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
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[(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
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Requires<[HasSSE2, OptForSize]>;
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// extload f32 -> f64. This matches load+fextend because we have a hack in
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// the isel (PreprocessForFPConvert) that can introduce loads after dag
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// combine.
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// Since these loads aren't folded into the fextend, we have to match it
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// explicitly here.
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def : Pat<(fextend (loadf32 addr:$src)),
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(CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
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def : Pat<(extloadf32 addr:$src),
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(CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
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@ -2449,63 +2523,6 @@ let Predicates = [HasAVX] in {
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OpSize, VEX;
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}
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
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//===----------------------------------------------------------------------===//
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// Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
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// names that start with 'Fs'.
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// Alias instructions that map fld0 to pxor for sse.
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// FIXME: Set encoding to pseudo!
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let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
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canFoldAsLoad = 1 in {
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def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
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[(set FR32:$dst, fp32imm0)]>,
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Requires<[HasSSE1]>, TB, OpSize;
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def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
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[(set FR64:$dst, fpimm0)]>,
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Requires<[HasSSE2]>, TB, OpSize;
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def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
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[(set FR32:$dst, fp32imm0)]>,
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Requires<[HasAVX]>, TB, OpSize, VEX_4V;
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def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
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[(set FR64:$dst, fpimm0)]>,
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Requires<[HasAVX]>, TB, OpSize, VEX_4V;
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}
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// Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
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// bits are disregarded. FIXME: Set encoding to pseudo!
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let neverHasSideEffects = 1 in {
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def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
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"movaps\t{$src, $dst|$dst, $src}", []>;
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def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
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"movapd\t{$src, $dst|$dst, $src}", []>;
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def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
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"movaps\t{$src, $dst|$dst, $src}", []>, VEX;
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def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
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"movapd\t{$src, $dst|$dst, $src}", []>, VEX;
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}
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// Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
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// bits are disregarded. FIXME: Set encoding to pseudo!
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let canFoldAsLoad = 1, isReMaterializable = 1 in {
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def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
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"movaps\t{$src, $dst|$dst, $src}",
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[(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
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def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
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"movapd\t{$src, $dst|$dst, $src}",
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[(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
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let isCodeGenOnly = 1 in {
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def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
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"movaps\t{$src, $dst|$dst, $src}",
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[(set FR32:$dst, (alignedloadfsf32 addr:$src))]>, VEX;
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def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
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"movapd\t{$src, $dst|$dst, $src}",
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[(set FR64:$dst, (alignedloadfsf64 addr:$src))]>, VEX;
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}
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}
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Logical Instructions
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//===----------------------------------------------------------------------===//
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@ -3113,10 +3130,26 @@ def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
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def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
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"prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
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// Flush cache
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def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
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"clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
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TB, Requires<[HasSSE2]>;
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// Pause. This "instruction" is encoded as "rep; nop", so even though it
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// was introduced with SSE2, it's backward compatible.
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def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
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// Load, store, and memory fence
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def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
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TB, Requires<[HasSSE1]>;
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def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
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"sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
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def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
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"lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
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def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
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"mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
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def : Pat<(X86SFence), (SFENCE)>;
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def : Pat<(X86LFence), (LFENCE)>;
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def : Pat<(X86MFence), (MFENCE)>;
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Load/Store XCSR register
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@ -4165,9 +4198,6 @@ def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
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[(store (i64 (vector_extract (v2i64 VR128:$src),
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(iPTR 0))), addr:$dst)]>;
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def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
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(f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
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//===---------------------------------------------------------------------===//
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// Store / copy lower 64-bits of a XMM register.
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//
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@ -4252,43 +4282,6 @@ def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"movq\t{$src, $dst|$dst, $src}", []>, XS;
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//===---------------------------------------------------------------------===//
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// SSE2 - Misc Instructions
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//===---------------------------------------------------------------------===//
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// Flush cache
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def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
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"clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
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TB, Requires<[HasSSE2]>;
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// Load, store, and memory fence
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def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
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"lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
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def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
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"mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
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def : Pat<(X86LFence), (LFENCE)>;
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def : Pat<(X86MFence), (MFENCE)>;
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// Pause. This "instruction" is encoded as "rep; nop", so even though it
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// was introduced with SSE2, it's backward compatible.
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def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
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// Alias instructions that map zero vector to pxor / xorp* for sse.
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// We set canFoldAsLoad because this can be converted to a constant-pool
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// load of an all-ones value if folding it would be beneficial.
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// FIXME: Change encoding to pseudo! This is blocked right now by the x86
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// JIT implementation, it does not expand the instructions below like
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// X86MCInstLower does.
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let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
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def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v4i32 immAllOnesV))]>;
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let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
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def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
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//===---------------------------------------------------------------------===//
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// SSE3 - Conversion Instructions
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//===---------------------------------------------------------------------===//
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@ -4816,10 +4809,9 @@ def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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}
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//===---------------------------------------------------------------------===//
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// SSSE3 Misc Instructions
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// SSSE3 - Thread synchronization
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//===---------------------------------------------------------------------===//
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// Thread synchronization
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let usesCustomInserter = 1 in {
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def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
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[(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
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@ -4842,15 +4834,6 @@ def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
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def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
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Requires<[In64BitMode]>;
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// extload f32 -> f64. This matches load+fextend because we have a hack in
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// the isel (PreprocessForFPConvert) that can introduce loads after dag
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// combine.
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// Since these loads aren't folded into the fextend, we have to match it
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// explicitly here.
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let Predicates = [HasSSE2] in
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def : Pat<(fextend (loadf32 addr:$src)),
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(CVTSS2SDrm addr:$src)>;
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// Splat v2f64 / v2i64
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let AddedComplexity = 10 in {
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def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
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