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AVX-512: Fixed a bug in shufflevector lowering. 

PALIGNR instruction does not exist in AVX-512F set.
Added a test.

llvm-svn: 215526
This commit is contained in:
Elena Demikhovsky 2014-08-13 07:58:43 +00:00
parent a4a4db91be
commit 51bbd011c3
2 changed files with 20 additions and 1 deletions
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3
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -3872,7 +3872,8 @@ static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT, static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
const X86Subtarget *Subtarget) { const X86Subtarget *Subtarget) {
if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) || if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
(VT.is256BitVector() && !Subtarget->hasInt256())) (VT.is256BitVector() && !Subtarget->hasInt256()) ||
VT.is512BitVector())
// FIXME: Add AVX512BW. // FIXME: Add AVX512BW.
return false; return false;

18
llvm/test/CodeGen/X86/avx512-shuffle.ll
View File

@ -199,6 +199,24 @@ define <16 x i32> @test15(<16 x i32> %a) {
%b = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32><i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> %b = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32><i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
ret <16 x i32> %b ret <16 x i32> %b
} }
; CHECK-LABEL: valign_test_v16f32
; CHECK: valignd $2, %zmm0, %zmm0
; CHECK: ret
define <16 x float> @valign_test_v16f32(<16 x float> %a, <16 x float> %b) nounwind {
%c = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32><i32 2, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 undef, i32 10, i32 11, i32 undef, i32 undef, i32 14, i32 15, i32 undef, i32 undef>
ret <16 x float> %c
}
; CHECK-LABEL: valign_test_v16i32
; CHECK: valignd $2, %zmm0, %zmm0
; CHECK: ret
define <16 x i32> @valign_test_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind {
%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32><i32 2, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 undef, i32 10, i32 11, i32 undef, i32 undef, i32 14, i32 15, i32 undef, i32 undef>
ret <16 x i32> %c
}
; CHECK-LABEL: test16 ; CHECK-LABEL: test16
; CHECK: valignq $2, %zmm0, %zmm1 ; CHECK: valignq $2, %zmm0, %zmm1
; CHECK: ret ; CHECK: ret