[x86] autoupgrade and remove SSE2/SSE41 integer min/max intrinsics
Follow-up to: http://reviews.llvm.org/rL272806 http://reviews.llvm.org/rL272807 llvm-svn: 272907
This commit is contained in:
Sanjay Patel
parent
8e3c74210f
commit
51ab757941
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@ -406,18 +406,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse2_pavg_w : GCCBuiltin<"__builtin_ia32_pavgw128">,
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Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
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llvm_v8i16_ty], [IntrNoMem, Commutative]>;
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def int_x86_sse2_pmaxu_b :
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,
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llvm_v16i8_ty], [IntrNoMem, Commutative]>;
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def int_x86_sse2_pmaxs_w :
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Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
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llvm_v8i16_ty], [IntrNoMem, Commutative]>;
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def int_x86_sse2_pminu_b :
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,
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llvm_v16i8_ty], [IntrNoMem, Commutative]>;
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def int_x86_sse2_pmins_w :
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Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
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llvm_v8i16_ty], [IntrNoMem, Commutative]>;
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def int_x86_sse2_psad_bw : GCCBuiltin<"__builtin_ia32_psadbw128">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v16i8_ty,
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llvm_v16i8_ty], [IntrNoMem, Commutative]>;
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@ -735,34 +723,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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[IntrNoMem]>;
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}
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// Vector compare, min, max
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse41_pmaxsb :
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
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[IntrNoMem, Commutative]>;
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def int_x86_sse41_pmaxsd :
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
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[IntrNoMem, Commutative]>;
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def int_x86_sse41_pmaxud :
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
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[IntrNoMem, Commutative]>;
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def int_x86_sse41_pmaxuw :
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Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
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[IntrNoMem, Commutative]>;
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def int_x86_sse41_pminsb :
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
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[IntrNoMem, Commutative]>;
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def int_x86_sse41_pminsd :
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
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[IntrNoMem, Commutative]>;
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def int_x86_sse41_pminud :
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
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[IntrNoMem, Commutative]>;
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def int_x86_sse41_pminuw :
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Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
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[IntrNoMem, Commutative]>;
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}
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// Advanced Encryption Standard (AES) Instructions
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_aesni_aesimc : GCCBuiltin<"__builtin_ia32_aesimc128">,
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@ -174,6 +174,18 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) {
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Name.startswith("x86.sse2.pcmpgt.") ||
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Name.startswith("x86.avx2.pcmpeq.") ||
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Name.startswith("x86.avx2.pcmpgt.") ||
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Name == "x86.sse41.pmaxsb" ||
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Name == "x86.sse2.pmaxs.w" ||
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Name == "x86.sse41.pmaxsd" ||
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Name == "x86.sse2.pmaxu.b" ||
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Name == "x86.sse41.pmaxuw" ||
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Name == "x86.sse41.pmaxud" ||
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Name == "x86.sse41.pminsb" ||
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Name == "x86.sse2.pmins.w" ||
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Name == "x86.sse41.pminsd" ||
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Name == "x86.sse2.pminu.b" ||
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Name == "x86.sse41.pminuw" ||
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Name == "x86.sse41.pminud" ||
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Name.startswith("x86.avx2.vbroadcast") ||
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Name.startswith("x86.avx2.pbroadcast") ||
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Name.startswith("x86.avx.vpermil.") ||
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@ -518,6 +530,14 @@ static Value *UpgradeMaskedLoad(IRBuilder<> &Builder, LLVMContext &C,
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return Builder.CreateMaskedLoad(Ptr, Align, Mask, Passthru);
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}
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static Value *upgradeIntMinMax(IRBuilder<> &Builder, CallInst &CI,
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ICmpInst::Predicate Pred) {
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Value *Op0 = CI.getArgOperand(0);
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Value *Op1 = CI.getArgOperand(1);
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Value *Cmp = Builder.CreateICmp(Pred, Op0, Op1);
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return Builder.CreateSelect(Cmp, Op0, Op1);
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}
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/// Upgrade a call to an old intrinsic. All argument and return casting must be
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/// provided to seamlessly integrate with existing context.
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void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
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@ -544,6 +564,22 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
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Rep = Builder.CreateICmpSGT(CI->getArgOperand(0), CI->getArgOperand(1),
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"pcmpgt");
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Rep = Builder.CreateSExt(Rep, CI->getType(), "");
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} else if (Name == "llvm.x86.sse41.pmaxsb" ||
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Name == "llvm.x86.sse2.pmaxs.w" ||
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Name == "llvm.x86.sse41.pmaxsd") {
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Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SGT);
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} else if (Name == "llvm.x86.sse2.pmaxu.b" ||
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Name == "llvm.x86.sse41.pmaxuw" ||
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Name == "llvm.x86.sse41.pmaxud") {
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Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_UGT);
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} else if (Name == "llvm.x86.sse41.pminsb" ||
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Name == "llvm.x86.sse2.pmins.w" ||
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Name == "llvm.x86.sse41.pminsd") {
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Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SLT);
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} else if (Name == "llvm.x86.sse2.pminu.b" ||
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Name == "llvm.x86.sse41.pminuw" ||
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Name == "llvm.x86.sse41.pminud") {
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Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_ULT);
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} else if (Name == "llvm.x86.sse2.cvtdq2pd" ||
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Name == "llvm.x86.sse2.cvtps2pd" ||
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Name == "llvm.x86.avx.cvtdq2.pd.256" ||
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@ -2104,10 +2104,6 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(sse2_paddus_w, INTR_TYPE_2OP, X86ISD::ADDUS, 0),
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X86_INTRINSIC_DATA(sse2_pavg_b, INTR_TYPE_2OP, X86ISD::AVG, 0),
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X86_INTRINSIC_DATA(sse2_pavg_w, INTR_TYPE_2OP, X86ISD::AVG, 0),
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X86_INTRINSIC_DATA(sse2_pmaxs_w, INTR_TYPE_2OP, ISD::SMAX, 0),
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X86_INTRINSIC_DATA(sse2_pmaxu_b, INTR_TYPE_2OP, ISD::UMAX, 0),
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X86_INTRINSIC_DATA(sse2_pmins_w, INTR_TYPE_2OP, ISD::SMIN, 0),
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X86_INTRINSIC_DATA(sse2_pminu_b, INTR_TYPE_2OP, ISD::UMIN, 0),
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X86_INTRINSIC_DATA(sse2_pmovmskb_128, INTR_TYPE_1OP, X86ISD::MOVMSK, 0),
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X86_INTRINSIC_DATA(sse2_pmulh_w, INTR_TYPE_2OP, ISD::MULHS, 0),
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X86_INTRINSIC_DATA(sse2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
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@ -2146,14 +2142,6 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(sse3_hsub_ps, INTR_TYPE_2OP, X86ISD::FHSUB, 0),
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X86_INTRINSIC_DATA(sse41_insertps, INTR_TYPE_3OP, X86ISD::INSERTPS, 0),
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X86_INTRINSIC_DATA(sse41_packusdw, INTR_TYPE_2OP, X86ISD::PACKUS, 0),
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X86_INTRINSIC_DATA(sse41_pmaxsb, INTR_TYPE_2OP, ISD::SMAX, 0),
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X86_INTRINSIC_DATA(sse41_pmaxsd, INTR_TYPE_2OP, ISD::SMAX, 0),
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X86_INTRINSIC_DATA(sse41_pmaxud, INTR_TYPE_2OP, ISD::UMAX, 0),
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X86_INTRINSIC_DATA(sse41_pmaxuw, INTR_TYPE_2OP, ISD::UMAX, 0),
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X86_INTRINSIC_DATA(sse41_pminsb, INTR_TYPE_2OP, ISD::SMIN, 0),
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X86_INTRINSIC_DATA(sse41_pminsd, INTR_TYPE_2OP, ISD::SMIN, 0),
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X86_INTRINSIC_DATA(sse41_pminud, INTR_TYPE_2OP, ISD::UMIN, 0),
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X86_INTRINSIC_DATA(sse41_pminuw, INTR_TYPE_2OP, ISD::UMIN, 0),
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X86_INTRINSIC_DATA(sse41_pmuldq, INTR_TYPE_2OP, X86ISD::PMULDQ, 0),
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X86_INTRINSIC_DATA(sse4a_extrqi, INTR_TYPE_3OP, X86ISD::EXTRQI, 0),
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X86_INTRINSIC_DATA(sse4a_insertqi, INTR_TYPE_4OP, X86ISD::INSERTQI, 0),
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@ -144,8 +144,8 @@ define <4 x i32> @test_x86_sse2_pshuf_d(<4 x i32> %a) {
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
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; CHECK-NEXT: retl
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entry:
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%res = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27) nounwind readnone
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ret <4 x i32> %res
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%res = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27) nounwind readnone
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32>, i8) nounwind readnone
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@ -155,8 +155,8 @@ define <8 x i16> @test_x86_sse2_pshufl_w(<8 x i16> %a) {
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; CHECK-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
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; CHECK-NEXT: retl
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entry:
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%res = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27) nounwind readnone
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ret <8 x i16> %res
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%res = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27) nounwind readnone
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8) nounwind readnone
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@ -166,7 +166,52 @@ define <8 x i16> @test_x86_sse2_pshufh_w(<8 x i16> %a) {
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; CHECK-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
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; CHECK-NEXT: retl
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entry:
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%res = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27) nounwind readnone
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ret <8 x i16> %res
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%res = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27) nounwind readnone
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8) nounwind readnone
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define <16 x i8> @max_epu8(<16 x i8> %a0, <16 x i8> %a1) {
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; CHECK-LABEL: max_epu8:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmaxub %xmm1, %xmm0
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; CHECK-NEXT: retl
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;
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%res = call <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8> %a0, <16 x i8> %a1)
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ret <16 x i8> %res
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}
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declare <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8>, <16 x i8>) nounwind readnone
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define <16 x i8> @min_epu8(<16 x i8> %a0, <16 x i8> %a1) {
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; CHECK-LABEL: min_epu8:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pminub %xmm1, %xmm0
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; CHECK-NEXT: retl
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;
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%res = call <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8> %a0, <16 x i8> %a1)
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ret <16 x i8> %res
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}
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declare <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8>, <16 x i8>) nounwind readnone
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define <8 x i16> @max_epi16(<8 x i16> %a0, <8 x i16> %a1) {
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; CHECK-LABEL: max_epi16:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmaxsw %xmm1, %xmm0
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; CHECK-NEXT: retl
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;
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%res = call <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16> %a0, <8 x i16> %a1)
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16>, <8 x i16>) nounwind readnone
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define <8 x i16> @min_epi16(<8 x i16> %a0, <8 x i16> %a1) {
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; CHECK-LABEL: min_epi16:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pminsw %xmm1, %xmm0
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; CHECK-NEXT: retl
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;
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%res = call <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16> %a0, <8 x i16> %a1)
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16>, <8 x i16>) nounwind readnone
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@ -1,4 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse4.1 | FileCheck %s
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; This test works just like the non-upgrade one except that it only checks
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@ -211,3 +211,92 @@ define <2 x i64> @test_x86_sse41_pmovzxwq(<8 x i16> %a0) {
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ret <2 x i64> %res
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}
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declare <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16>) nounwind readnone
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define <16 x i8> @max_epi8(<16 x i8> %a0, <16 x i8> %a1) {
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; CHECK-LABEL: max_epi8:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmaxsb %xmm1, %xmm0
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; CHECK-NEXT: retl
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;
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%res = call <16 x i8> @llvm.x86.sse41.pmaxsb(<16 x i8> %a0, <16 x i8> %a1)
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ret <16 x i8> %res
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}
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declare <16 x i8> @llvm.x86.sse41.pmaxsb(<16 x i8>, <16 x i8>) nounwind readnone
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define <16 x i8> @min_epi8(<16 x i8> %a0, <16 x i8> %a1) {
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; CHECK-LABEL: min_epi8:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pminsb %xmm1, %xmm0
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; CHECK-NEXT: retl
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;
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%res = call <16 x i8> @llvm.x86.sse41.pminsb(<16 x i8> %a0, <16 x i8> %a1)
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ret <16 x i8> %res
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}
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declare <16 x i8> @llvm.x86.sse41.pminsb(<16 x i8>, <16 x i8>) nounwind readnone
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define <8 x i16> @max_epu16(<8 x i16> %a0, <8 x i16> %a1) {
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; CHECK-LABEL: max_epu16:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmaxuw %xmm1, %xmm0
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; CHECK-NEXT: retl
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;
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%res = call <8 x i16> @llvm.x86.sse41.pmaxuw(<8 x i16> %a0, <8 x i16> %a1)
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.sse41.pmaxuw(<8 x i16>, <8 x i16>) nounwind readnone
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define <8 x i16> @min_epu16(<8 x i16> %a0, <8 x i16> %a1) {
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; CHECK-LABEL: min_epu16:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pminuw %xmm1, %xmm0
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; CHECK-NEXT: retl
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;
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%res = call <8 x i16> @llvm.x86.sse41.pminuw(<8 x i16> %a0, <8 x i16> %a1)
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.sse41.pminuw(<8 x i16>, <8 x i16>) nounwind readnone
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define <4 x i32> @max_epi32(<4 x i32> %a0, <4 x i32> %a1) {
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; CHECK-LABEL: max_epi32:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmaxsd %xmm1, %xmm0
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; CHECK-NEXT: retl
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;
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%res = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a0, <4 x i32> %a1)
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone
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define <4 x i32> @min_epi32(<4 x i32> %a0, <4 x i32> %a1) {
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; CHECK-LABEL: min_epi32:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pminsd %xmm1, %xmm0
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; CHECK-NEXT: retl
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;
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%res = call <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32> %a0, <4 x i32> %a1)
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32>, <4 x i32>) nounwind readnone
|
||||
|
||||
define <4 x i32> @max_epu32(<4 x i32> %a0, <4 x i32> %a1) {
|
||||
; CHECK-LABEL: max_epu32:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: pmaxud %xmm1, %xmm0
|
||||
; CHECK-NEXT: retl
|
||||
;
|
||||
%res = call <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32> %a0, <4 x i32> %a1)
|
||||
ret <4 x i32> %res
|
||||
}
|
||||
declare <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32>, <4 x i32>) nounwind readnone
|
||||
|
||||
define <4 x i32> @min_epu32(<4 x i32> %a0, <4 x i32> %a1) {
|
||||
; CHECK-LABEL: min_epu32:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: pminud %xmm1, %xmm0
|
||||
; CHECK-NEXT: retl
|
||||
;
|
||||
%res = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %a0, <4 x i32> %a1)
|
||||
ret <4 x i32> %res
|
||||
}
|
||||
declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>) nounwind readnone
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue