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Add PREFETCHW codegen support 

- Add 'PRFCHW' feature defined in AVX2 ISA extension

llvm-svn: 178040
This commit is contained in:
Michael Liao 2013-03-26 17:47:11 +00:00
parent bce7c77d85
commit 5173ee03af
6 changed files with 24 additions and 5 deletions
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2
llvm/lib/Target/X86/X86.td
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@ -122,6 +122,8 @@ def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
"Support RTM instructions">;
def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
"Support ADX instructions">;
def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
"Support PRFCHW instructions">;
def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
"Use LEA for adjusting the stack pointer">;
def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb",

13
llvm/lib/Target/X86/X86Instr3DNow.td
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@ -84,13 +84,16 @@ defm PI2FD : I3DNow_conv_rm_int<0x0D, "pi2fd">;
defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw">;
def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>;
def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms",
[(int_x86_mmx_femms)]>;
def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i32mem:$addr),
"prefetch\t$addr", []>;
def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr),
"prefetch\t$addr",
[(prefetch addr:$addr, (i32 0), imm, (i32 1))]>;
def PREFETCHW : I3DNow<0x0D, MRM1m, (outs), (ins i16mem:$addr),
"prefetchw\t$addr", []>;
def PREFETCHW : I<0x0D, MRM1m, (outs), (ins i8mem:$addr), "prefetchw\t$addr",
[(prefetch addr:$addr, (i32 1), (i32 3), (i32 1))]>, TB,
Requires<[HasPrefetchW]>;
// "3DNowA" instructions
defm PF2IW : I3DNow_conv_rm_int<0x1C, "pf2iw", "a">;

2
llvm/lib/Target/X86/X86InstrInfo.td
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@ -604,6 +604,8 @@ def HasBMI : Predicate<"Subtarget->hasBMI()">;
def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
def HasRTM : Predicate<"Subtarget->hasRTM()">;
def HasADX : Predicate<"Subtarget->hasADX()">;
def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
def HasPrefetchW : Predicate<"Subtarget->has3DNow() || Subtarget->hasPRFCHW()">;
def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;

5
llvm/lib/Target/X86/X86Subtarget.cpp
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@ -283,6 +283,10 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
HasLZCNT = true;
ToggleFeature(X86::FeatureLZCNT);
}
if (IsIntel && ((ECX >> 8) & 0x1)) {
HasPRFCHW = true;
ToggleFeature(X86::FeaturePRFCHW);
}
if (IsAMD) {
if ((ECX >> 6) & 0x1) {
HasSSE4A = true;
@ -440,6 +444,7 @@ void X86Subtarget::initializeEnvironment() {
HasBMI2 = false;
HasRTM = false;
HasADX = false;
HasPRFCHW = false;
IsBTMemSlow = false;
IsUAMemFast = false;
HasVectorUAMem = false;

4
llvm/lib/Target/X86/X86Subtarget.h
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@ -124,6 +124,9 @@ protected:
/// HasADX - Processor has ADX instructions.
bool HasADX;
/// HasPRFCHW - Processor has PRFCHW instructions.
bool HasPRFCHW;
/// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
bool IsBTMemSlow;
@ -254,6 +257,7 @@ public:
bool hasBMI2() const { return HasBMI2; }
bool hasRTM() const { return HasRTM; }
bool hasADX() const { return HasADX; }
bool hasPRFCHW() const { return HasPRFCHW; }
bool isBTMemSlow() const { return IsBTMemSlow; }
bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
bool hasVectorUAMem() const { return HasVectorUAMem; }

3
llvm/test/CodeGen/X86/prefetch.ll
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@ -1,5 +1,6 @@
; RUN: llc < %s -march=x86 -mattr=+sse | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+prfchw | FileCheck %s -check-prefix=PRFCHW
; rdar://10538297
@ -9,10 +10,12 @@ entry:
; CHECK: prefetcht1
; CHECK: prefetcht0
; CHECK: prefetchnta
; PRFCHW: prefetchw
tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1, i32 1 )
tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2, i32 1 )
tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 )
tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0, i32 1 )
tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3, i32 1 )
ret void
}