[X86][SSE] Added load_zext_16i8_to_8i32 test
Odd issue with input vector not being folded into pmovzx on AVX2+ targets llvm-svn: 270852
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@ -667,6 +667,62 @@ entry:
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ret <8 x i32> %Y
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}
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define <8 x i32> @load_zext_16i8_to_8i32(<16 x i8> *%ptr) {
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; SSE2-LABEL: load_zext_16i8_to_8i32:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movdqa (%rdi), %xmm1
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; SSE2-NEXT: pxor %xmm2, %xmm2
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
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; SSE2-NEXT: movdqa %xmm1, %xmm0
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
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; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: load_zext_16i8_to_8i32:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movdqa (%rdi), %xmm1
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; SSSE3-NEXT: pxor %xmm2, %xmm2
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; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
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; SSSE3-NEXT: movdqa %xmm1, %xmm0
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; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
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; SSSE3-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: load_zext_16i8_to_8i32:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: movdqa (%rdi), %xmm1
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; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
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; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,2,3]
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; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: load_zext_16i8_to_8i32:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vmovdqa (%rdi), %xmm0
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; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
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; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: load_zext_16i8_to_8i32:
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; AVX2: # BB#0: # %entry
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; AVX2-NEXT: vmovdqa (%rdi), %xmm0
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; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: load_zext_16i8_to_8i32:
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; AVX512: # BB#0: # %entry
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; AVX512-NEXT: vmovdqa (%rdi), %xmm0
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; AVX512-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
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; AVX512-NEXT: retq
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entry:
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%X = load <16 x i8>, <16 x i8>* %ptr
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%Y = shufflevector <16 x i8> %X, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%Z = zext <8 x i8> %Y to <8 x i32>
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ret <8 x i32> %Z
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}
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define <8 x i64> @load_zext_8i8_to_8i64(<8 x i8> *%ptr) {
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; SSE2-LABEL: load_zext_8i8_to_8i64:
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; SSE2: # BB#0: # %entry
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