parent
61fafd35f5
commit
4fbd8a2f78
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@ -379,6 +379,25 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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O << "\n";
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return;
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}
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case X86II::MRMDestMem: {
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// These instructions are the same as MRMDestReg, but instead of having a
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// register reference for the mod/rm field, it's a memory reference.
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//
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assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
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isReg(MI->getOperand(4)) && "Bad format for MRMDestMem!");
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toHex(O, getBaseOpcodeFor(Opcode)) << " ";
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emitMemModRMByte(O, MI, 0, getX86RegNum(MI->getOperand(4).getReg()));
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O << "\n\t\t\t\t";
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O << getName(MI->getOpCode()) << " <SIZE> PTR ";
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printMemReference(O, MI, 0, RI);
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O << ", ";
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printOp(O, MI->getOperand(4), RI);
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O << "\n";
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return;
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}
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case X86II::MRMSrcReg: {
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// There is a two forms that are acceptable for MRMSrcReg instructions,
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// those with 3 and 2 operands:
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@ -415,10 +434,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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case X86II::MRMSrcMem: {
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// These instructions are the same as MRMSrcReg, but instead of having a
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// register reference for the mod/rm field, it's a memory reference.
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//I(MOVmr8 , "movb", 0x8A, 0, X86II::MRMSrcMem)
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// R8 = [mem] 8A/r
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//
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assert(isReg(MI->getOperand(0)) &&
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(MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
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(MI->getNumOperands() == 2+4 && isReg(MI->getOperand(1)) &&
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@ -483,7 +499,6 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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return;
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}
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case X86II::MRMDestMem:
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default:
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O << "\t\t\t-"; MI->print(O, TM); break;
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}
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