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Add code to emulate LDRH (register) Arm instruction. 

llvm-svn: 126758
This commit is contained in:
Caroline Tice 2011-03-01 18:00:42 +00:00
parent ee8188a23b
commit 4f0e5f8852
1 changed files with 181 additions and 2 deletions
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181
lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
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@ -6041,7 +6041,6 @@ EmulateInstructionARM::EmulateLDRHLiteral (ARMEncoding encoding)
R[t] = bits(32) UNKNOWN;
#endif
bool success = false;
const uint32_t opcode = OpcodeAsUnsigned (&success);
if (!success)
@ -6135,6 +6134,183 @@ EmulateInstructionARM::EmulateLDRHLiteral (ARMEncoding encoding)
return true;
}
// LDRH (literal) calculates an address from a base register value and an offset register value, loads a halfword
// from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can
// be shifted left by 0, 1, 2, or 3 bits.
bool
EmulateInstructionARM::EmulateLDRHRegister (ARMEncoding encoding)
{
#if 0
if ConditionPassed() then
EncodingSpecificOperations(); NullCheckIfThumbEE(n);
offset = Shift(R[m], shift_t, shift_n, APSR.C);
offset_addr = if add then (R[n] + offset) else (R[n] - offset);
address = if index then offset_addr else R[n];
data = MemU[address,2];
if wback then R[n] = offset_addr;
if UnalignedSupport() || address<0> = ’0’ then
R[t] = ZeroExtend(data, 32);
else // Can only apply before ARMv7
R[t] = bits(32) UNKNOWN;
#endif
bool success = false;
const uint32_t opcode = OpcodeAsUnsigned (&success);
if (!success)
return false;
if (ConditionPassed())
{
uint32_t t;
uint32_t n;
uint32_t m;
bool index;
bool add;
bool wback;
ARM_ShifterType shift_t;
uint32_t shift_n;
// EncodingSpecificOperations(); NullCheckIfThumbEE(n);
switch (encoding)
{
case eEncodingT1:
// if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
// t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
t = Bits32 (opcode, 2, 0);
n = Bits32 (opcode, 5, 3);
m = Bits32 (opcode, 8, 6);
// index = TRUE; add = TRUE; wback = FALSE;
index = true;
add = true;
wback = false;
// (shift_t, shift_n) = (SRType_LSL, 0);
shift_t = SRType_LSL;
shift_n = 0;
break;
case eEncodingT2:
// if Rn == ’1111’ then SEE LDRH (literal);
// if Rt == ’1111’ then SEE "Unallocated memory hints";
// t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
t = Bits32 (opcode, 15, 12);
n = Bits32 (opcode, 19, 16);
m = Bits32 (opcode, 3, 0);
// index = TRUE; add = TRUE; wback = FALSE;
index = true;
add = true;
wback = false;
// (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
shift_t = SRType_LSL;
shift_n = Bits32 (opcode, 5, 4);
// if t == 13 || BadReg(m) then UNPREDICTABLE;
if ((t == 13) || BadReg (m))
return false;
break;
case eEncodingA1:
// if P == ’0’ && W == ’1’ then SEE LDRHT;
// t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
t = Bits32 (opcode, 15, 12);
n = Bits32 (opcode, 19, 16);
m = Bits32 (opcode, 3, 0);
// index = (P == ’1’); add = (U == ’1’); wback = (P == ’0’) || (W == ’1’);
index = BitIsSet (opcode, 24);
add = BitIsSet (opcode, 23);
wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
// (shift_t, shift_n) = (SRType_LSL, 0);
shift_t = SRType_LSL;
shift_n = 0;
// if t == 15 || m == 15 then UNPREDICTABLE;
if ((t == 15) || (m == 15))
return false;
// if wback && (n == 15 || n == t) then UNPREDICTABLE;
if (wback && ((n == 15) || (n == t)))
return false;
break;
default:
return false;
}
// offset = Shift(R[m], shift_t, shift_n, APSR.C);
uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
if (!success)
return false;
addr_t offset = Shift (Rm, shift_t, shift_n, APSR_C);
addr_t offset_addr;
addr_t address;
// offset_addr = if add then (R[n] + offset) else (R[n] - offset);
uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
if (!success)
return false;
if (add)
offset_addr = Rn + offset;
else
offset_addr = Rn - offset;
// address = if index then offset_addr else R[n];
if (index)
address = offset_addr;
else
address = Rn;
// data = MemU[address,2];
Register base_reg;
Register offset_reg;
base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
offset_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
context.SetRegisterPlusIndirectOffset (base_reg, offset_reg);
uint64_t data = MemURead (context, address, 2, 0, &success);
if (!success)
return false;
// if wback then R[n] = offset_addr;
if (wback)
{
context.type = eContextAdjustBaseRegister;
context.SetAddress (offset_addr);
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
return false;
}
// if UnalignedSupport() || address<0> = ’0’ then
if (UnalignedSupport() || BitIsClear (address, 0))
{
// R[t] = ZeroExtend(data, 32);
context.type = eContextRegisterLoad;
context.SetRegisterPlusIndirectOffset (base_reg, offset_reg);
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
return false;
}
else // Can only apply before ARMv7
{
// R[t] = bits(32) UNKNOWN;
WriteBits32Unknown (t);
}
}
return true;
}
// Bitwise Exclusive OR (immediate) performs a bitwise exclusive OR of a register value and an immediate value,
// and writes the result to the destination register. It can optionally update the condition flags based on
// the result.
@ -7508,6 +7684,7 @@ EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode)
{ 0x0e5f0000, 0x045f0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRBLiteral, "ldrb<c> <Rt>, [...]"},
{ 0xfe500010, 0x06500000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c> <Rt>, [<Rn>,+/-<Rm>{, <shift>}]{!}" },
{ 0x0e5f00f0, 0x005f00b0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRHLiteral, "ldrh<c> <Rt>, <label>" },
{ 0x0e5000f0, 0x001000b0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
//----------------------------------------------------------------------
// Store instructions
@ -7750,6 +7927,8 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode)
{ 0xfff00000, 0xf8b00000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c>.w <Rt>,[<Rn>{,#<imm12>}]" },
{ 0xfff00800, 0xf8300800, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c> <Rt>,[<Rn>,#+/-<imm8>]{!}" },
{ 0xff7f0000, 0xf83f0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateLDRHLiteral, "ldrh<c> <Rt>, <label>" },
{ 0xfffffe00, 0x00005a00, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c> <Rt>, [<Rn>,<Rm>]" },
{ 0xfff00fc0, 0xf8300000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" },
//----------------------------------------------------------------------
// Store instructions