Add code to emulate LDRH (register) Arm instruction.
llvm-svn: 126758
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@ -6040,8 +6040,7 @@ EmulateInstructionARM::EmulateLDRHLiteral (ARMEncoding encoding)
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else // Can only apply before ARMv7
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R[t] = bits(32) UNKNOWN;
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#endif
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bool success = false;
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const uint32_t opcode = OpcodeAsUnsigned (&success);
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if (!success)
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@ -6135,6 +6134,183 @@ EmulateInstructionARM::EmulateLDRHLiteral (ARMEncoding encoding)
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return true;
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}
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// LDRH (literal) calculates an address from a base register value and an offset register value, loads a halfword
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// from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can
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// be shifted left by 0, 1, 2, or 3 bits.
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bool
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EmulateInstructionARM::EmulateLDRHRegister (ARMEncoding encoding)
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{
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#if 0
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if ConditionPassed() then
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EncodingSpecificOperations(); NullCheckIfThumbEE(n);
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offset = Shift(R[m], shift_t, shift_n, APSR.C);
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offset_addr = if add then (R[n] + offset) else (R[n] - offset);
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address = if index then offset_addr else R[n];
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data = MemU[address,2];
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if wback then R[n] = offset_addr;
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if UnalignedSupport() || address<0> = ’0’ then
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R[t] = ZeroExtend(data, 32);
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else // Can only apply before ARMv7
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R[t] = bits(32) UNKNOWN;
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#endif
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bool success = false;
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const uint32_t opcode = OpcodeAsUnsigned (&success);
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if (!success)
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return false;
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if (ConditionPassed())
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{
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uint32_t t;
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uint32_t n;
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uint32_t m;
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bool index;
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bool add;
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bool wback;
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ARM_ShifterType shift_t;
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uint32_t shift_n;
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// EncodingSpecificOperations(); NullCheckIfThumbEE(n);
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switch (encoding)
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{
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case eEncodingT1:
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// if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
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// t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
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t = Bits32 (opcode, 2, 0);
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n = Bits32 (opcode, 5, 3);
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m = Bits32 (opcode, 8, 6);
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// index = TRUE; add = TRUE; wback = FALSE;
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index = true;
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add = true;
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wback = false;
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// (shift_t, shift_n) = (SRType_LSL, 0);
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shift_t = SRType_LSL;
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shift_n = 0;
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break;
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case eEncodingT2:
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// if Rn == ’1111’ then SEE LDRH (literal);
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// if Rt == ’1111’ then SEE "Unallocated memory hints";
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// t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
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t = Bits32 (opcode, 15, 12);
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n = Bits32 (opcode, 19, 16);
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m = Bits32 (opcode, 3, 0);
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// index = TRUE; add = TRUE; wback = FALSE;
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index = true;
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add = true;
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wback = false;
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// (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
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shift_t = SRType_LSL;
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shift_n = Bits32 (opcode, 5, 4);
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// if t == 13 || BadReg(m) then UNPREDICTABLE;
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if ((t == 13) || BadReg (m))
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return false;
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break;
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case eEncodingA1:
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// if P == ’0’ && W == ’1’ then SEE LDRHT;
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// t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
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t = Bits32 (opcode, 15, 12);
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n = Bits32 (opcode, 19, 16);
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m = Bits32 (opcode, 3, 0);
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// index = (P == ’1’); add = (U == ’1’); wback = (P == ’0’) || (W == ’1’);
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index = BitIsSet (opcode, 24);
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add = BitIsSet (opcode, 23);
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wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
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// (shift_t, shift_n) = (SRType_LSL, 0);
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shift_t = SRType_LSL;
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shift_n = 0;
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// if t == 15 || m == 15 then UNPREDICTABLE;
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if ((t == 15) || (m == 15))
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return false;
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// if wback && (n == 15 || n == t) then UNPREDICTABLE;
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if (wback && ((n == 15) || (n == t)))
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return false;
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break;
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default:
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return false;
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}
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// offset = Shift(R[m], shift_t, shift_n, APSR.C);
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uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
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if (!success)
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return false;
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addr_t offset = Shift (Rm, shift_t, shift_n, APSR_C);
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addr_t offset_addr;
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addr_t address;
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// offset_addr = if add then (R[n] + offset) else (R[n] - offset);
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uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
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if (!success)
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return false;
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if (add)
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offset_addr = Rn + offset;
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else
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offset_addr = Rn - offset;
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// address = if index then offset_addr else R[n];
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if (index)
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address = offset_addr;
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else
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address = Rn;
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// data = MemU[address,2];
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Register base_reg;
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Register offset_reg;
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base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
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offset_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m);
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EmulateInstruction::Context context;
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context.type = eContextRegisterLoad;
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context.SetRegisterPlusIndirectOffset (base_reg, offset_reg);
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uint64_t data = MemURead (context, address, 2, 0, &success);
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if (!success)
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return false;
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// if wback then R[n] = offset_addr;
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if (wback)
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{
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context.type = eContextAdjustBaseRegister;
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context.SetAddress (offset_addr);
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if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
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return false;
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}
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// if UnalignedSupport() || address<0> = ’0’ then
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if (UnalignedSupport() || BitIsClear (address, 0))
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{
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// R[t] = ZeroExtend(data, 32);
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context.type = eContextRegisterLoad;
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context.SetRegisterPlusIndirectOffset (base_reg, offset_reg);
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if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
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return false;
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}
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else // Can only apply before ARMv7
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{
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// R[t] = bits(32) UNKNOWN;
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WriteBits32Unknown (t);
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}
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}
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return true;
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}
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// Bitwise Exclusive OR (immediate) performs a bitwise exclusive OR of a register value and an immediate value,
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// and writes the result to the destination register. It can optionally update the condition flags based on
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// the result.
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@ -7508,6 +7684,7 @@ EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode)
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{ 0x0e5f0000, 0x045f0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRBLiteral, "ldrb<c> <Rt>, [...]"},
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{ 0xfe500010, 0x06500000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c> <Rt>, [<Rn>,+/-<Rm>{, <shift>}]{!}" },
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{ 0x0e5f00f0, 0x005f00b0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRHLiteral, "ldrh<c> <Rt>, <label>" },
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{ 0x0e5000f0, 0x001000b0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
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//----------------------------------------------------------------------
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// Store instructions
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@ -7750,6 +7927,8 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode)
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{ 0xfff00000, 0xf8b00000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c>.w <Rt>,[<Rn>{,#<imm12>}]" },
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{ 0xfff00800, 0xf8300800, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c> <Rt>,[<Rn>,#+/-<imm8>]{!}" },
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{ 0xff7f0000, 0xf83f0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateLDRHLiteral, "ldrh<c> <Rt>, <label>" },
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{ 0xfffffe00, 0x00005a00, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c> <Rt>, [<Rn>,<Rm>]" },
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{ 0xfff00fc0, 0xf8300000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" },
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//----------------------------------------------------------------------
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// Store instructions
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