Lowercase "is" boolean variable prefix for consistency within function, no functionality change.
llvm-svn: 180136
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5a348a12bd
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4eedb29b05
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@ -1368,22 +1368,22 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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bool isVarArg = CLI.IsVarArg;
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MachineFunction &MF = DAG.getMachineFunction();
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bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
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bool IsThisReturn = false;
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bool IsSibCall = false;
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bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
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bool isThisReturn = false;
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bool isSibCall = false;
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// Disable tail calls if they're not supported.
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if (!EnableARMTailCalls && !Subtarget->supportsTailCall())
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isTailCall = false;
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if (isTailCall) {
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// Check if it's really possible to do a tail call.
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isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
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isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
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isVarArg, isStructRet, MF.getFunction()->hasStructRetAttr(),
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Outs, OutVals, Ins, DAG);
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// We don't support GuaranteedTailCallOpt for ARM, only automatically
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// detected sibcalls.
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if (isTailCall) {
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++NumTailCalls;
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IsSibCall = true;
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isSibCall = true;
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}
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}
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@ -1399,12 +1399,12 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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unsigned NumBytes = CCInfo.getNextStackOffset();
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// For tail calls, memory operands are available in our caller's stack.
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if (IsSibCall)
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if (isSibCall)
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NumBytes = 0;
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// Adjust the stack pointer for the new arguments...
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// These operations are automatically eliminated by the prolog/epilog pass
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if (!IsSibCall)
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if (!isSibCall)
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
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SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
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@ -1469,7 +1469,7 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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if (realArgIdx == 0 && Flags.isReturned() && VA.getLocVT() == MVT::i32) {
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assert(!Ins.empty() && Ins[0].VT == Outs[0].VT &&
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"unexpected use of 'returned'");
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IsThisReturn = true;
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isThisReturn = true;
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}
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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} else if (isByVal) {
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@ -1510,7 +1510,7 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
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Ops, array_lengthof(Ops)));
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}
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} else if (!IsSibCall) {
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} else if (!isSibCall) {
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assert(VA.isMemLoc());
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MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
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@ -1694,7 +1694,7 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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const uint32_t *Mask;
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const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
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const ARMBaseRegisterInfo *ARI = static_cast<const ARMBaseRegisterInfo*>(TRI);
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if (IsThisReturn)
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if (isThisReturn)
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// For 'this' returns, use the R0-preserving mask
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Mask = ARI->getThisReturnPreservedMask(CallConv);
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else
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@ -1722,8 +1722,8 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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// Handle result values, copying them out of physregs into vregs that we
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// return.
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return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
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InVals, IsThisReturn,
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IsThisReturn ? OutVals[0] : SDValue());
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InVals, isThisReturn,
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isThisReturn ? OutVals[0] : SDValue());
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}
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/// HandleByVal - Every parameter *after* a byval parameter is passed
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