[PowerPC] Add PowerPC population count, reversed load and store related builtins and instrinsics for XL compatibility
This patch is in a series of patches to provide builtins for compatibility with the XL compiler. This patch adds the builtins and instrisics for population count, reversed load and store related operations. Reviewed By: nemanjai, #powerpc Differential revision: https://reviews.llvm.org/D106021
This commit is contained in:
Victor Huang
parent
ca662297d5
commit
4eb107ccba
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@ -31,6 +31,8 @@
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// builtins for compatibility with the XL compiler
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BUILTIN(__builtin_ppc_popcntb, "ULiULi", "")
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BUILTIN(__builtin_ppc_poppar4, "iUi", "")
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BUILTIN(__builtin_ppc_poppar8, "iULLi", "")
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BUILTIN(__builtin_ppc_eieio, "v", "")
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BUILTIN(__builtin_ppc_iospace_eieio, "v", "")
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BUILTIN(__builtin_ppc_isync, "v", "")
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@ -87,6 +89,14 @@ BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "")
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BUILTIN(__builtin_ppc_rlwnm, "UiUiIUiIUi", "")
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BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "")
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BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "")
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// load
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BUILTIN(__builtin_ppc_load2r, "UiUs*", "")
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BUILTIN(__builtin_ppc_load4r, "UiUi*", "")
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BUILTIN(__builtin_ppc_load8r, "ULLiULLi*", "")
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// store
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BUILTIN(__builtin_ppc_store2r, "vUiUs*", "")
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BUILTIN(__builtin_ppc_store4r, "vUiUi*", "")
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BUILTIN(__builtin_ppc_store8r, "vULLiULLi*", "")
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BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
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@ -89,6 +89,8 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
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static void defineXLCompatMacros(MacroBuilder &Builder) {
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Builder.defineMacro("__popcntb", "__builtin_ppc_popcntb");
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Builder.defineMacro("__poppar4", "__builtin_ppc_poppar4");
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Builder.defineMacro("__poppar8", "__builtin_ppc_poppar8");
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Builder.defineMacro("__eieio", "__builtin_ppc_eieio");
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Builder.defineMacro("__iospace_eieio", "__builtin_ppc_iospace_eieio");
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Builder.defineMacro("__isync", "__builtin_ppc_isync");
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@ -143,6 +145,12 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
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Builder.defineMacro("__rlwnm", "__builtin_ppc_rlwnm");
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Builder.defineMacro("__rlwimi", "__builtin_ppc_rlwimi");
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Builder.defineMacro("__rldimi", "__builtin_ppc_rldimi");
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Builder.defineMacro("__load2r", "__builtin_ppc_load2r");
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Builder.defineMacro("__load4r", "__builtin_ppc_load4r");
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Builder.defineMacro("__load8r", "__builtin_ppc_load8r");
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Builder.defineMacro("__store2r", "__builtin_ppc_store2r");
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Builder.defineMacro("__store4r", "__builtin_ppc_store4r");
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Builder.defineMacro("__store8r", "__builtin_ppc_store8r");
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}
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/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
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@ -15197,6 +15197,20 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID,
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Value *Shift = Builder.CreateCall(F, {Ops[0], Ops[0], Ops[1]});
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return Builder.CreateAnd(Shift, Ops[2]);
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}
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case PPC::BI__builtin_ppc_poppar4:
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case PPC::BI__builtin_ppc_poppar8: {
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llvm::Type *ArgType = Ops[0]->getType();
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Function *F = CGM.getIntrinsic(Intrinsic::ctpop, ArgType);
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Value *Tmp = Builder.CreateCall(F, Ops[0]);
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llvm::Type *ResultType = ConvertType(E->getType());
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Value *Result = Builder.CreateAnd(Tmp, llvm::ConstantInt::get(ArgType, 1));
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if (Result->getType() != ResultType)
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Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true,
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"cast");
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return Result;
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}
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// Copy sign
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case PPC::BI__builtin_vsx_xvcpsgnsp:
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case PPC::BI__builtin_vsx_xvcpsgndp: {
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@ -3276,6 +3276,8 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
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case PPC::BI__builtin_ppc_maddhd:
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case PPC::BI__builtin_ppc_maddhdu:
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case PPC::BI__builtin_ppc_maddld:
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case PPC::BI__builtin_ppc_load8r:
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case PPC::BI__builtin_ppc_store8r:
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return true;
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}
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return false;
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@ -0,0 +1,35 @@
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// REQUIRES: powerpc-registered-target.
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// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
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// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
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// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
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// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
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// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
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// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
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// RUN: not %clang_cc1 -triple powerpc-unknown-aix \
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// RUN: -emit-llvm %s -o - -target-cpu pwr7 2>&1 | FileCheck %s --check-prefix=CHECK-32-ERROR
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extern unsigned long long ull;
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extern unsigned long long *ull_addr;
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// CHECK-LABEL: @test_builtin_ppc_store8r(
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// CHECK: [[TMP0:%.*]] = load i64, i64* @ull, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load i64*, i64** @ull_addr, align 8
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// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64* [[TMP1]] to i8*
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// CHECK-NEXT: call void @llvm.ppc.store8r(i64 [[TMP0]], i8* [[TMP2]])
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// CHECK-NEXT: ret void
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// CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
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void test_builtin_ppc_store8r() {
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__builtin_ppc_store8r(ull, ull_addr);
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}
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// CHECK-LABEL: @test_builtin_ppc_load8r(
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// CHECK: [[TMP0:%.*]] = load i64*, i64** @ull_addr, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64* [[TMP0]] to i8*
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// CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.ppc.load8r(i8* [[TMP1]])
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// CHECK-NEXT: ret i64 [[TMP2]]
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// CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
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unsigned long long test_builtin_ppc_load8r() {
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return __builtin_ppc_load8r(ull_addr);
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}
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@ -0,0 +1,86 @@
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// REQUIRES: powerpc-registered-target.
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// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
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// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
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// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
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// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
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// RUN: %clang_cc1 -triple powerpc-unknown-aix \
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// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefixes=CHECK-32B
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// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
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// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
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extern unsigned short us;
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extern unsigned int ui;
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extern unsigned short *us_addr;
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extern unsigned int *ui_addr;
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// CHECK-LABEL: @test_builtin_ppc_store2r(
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// CHECK: [[TMP0:%.*]] = load i16, i16* @us, align 2
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// CHECK-NEXT: [[CONV:%.*]] = zext i16 [[TMP0]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = load i16*, i16** @us_addr, align 8
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// CHECK-NEXT: [[TMP2:%.*]] = bitcast i16* [[TMP1]] to i8*
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// CHECK-NEXT: call void @llvm.ppc.store2r(i32 [[CONV]], i8* [[TMP2]])
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// CHECK-NEXT: ret void
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//
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// CHECK-32B-LABEL: @test_builtin_ppc_store2r(
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// CHECK-32B: [[TMP0:%.*]] = load i16, i16* @us, align 2
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// CHECK-32B-NEXT: [[CONV:%.*]] = zext i16 [[TMP0]] to i32
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// CHECK-32B-NEXT: [[TMP1:%.*]] = load i16*, i16** @us_addr, align 4
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// CHECK-32B-NEXT: [[TMP2:%.*]] = bitcast i16* [[TMP1]] to i8*
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// CHECK-32B-NEXT: call void @llvm.ppc.store2r(i32 [[CONV]], i8* [[TMP2]])
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// CHECK-32B-NEXT: ret void
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//
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void test_builtin_ppc_store2r() {
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__builtin_ppc_store2r(us, us_addr);
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}
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// CHECK-LABEL: @test_builtin_ppc_store4r(
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// CHECK: [[TMP0:%.*]] = load i32, i32* @ui, align 4
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// CHECK-NEXT: [[TMP1:%.*]] = load i32*, i32** @ui_addr, align 8
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// CHECK-NEXT: [[TMP2:%.*]] = bitcast i32* [[TMP1]] to i8*
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// CHECK-NEXT: call void @llvm.ppc.store4r(i32 [[TMP0]], i8* [[TMP2]])
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// CHECK-NEXT: ret void
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//
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// CHECK-32B-LABEL: @test_builtin_ppc_store4r(
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// CHECK-32B: [[TMP0:%.*]] = load i32, i32* @ui, align 4
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// CHECK-32B-NEXT: [[TMP1:%.*]] = load i32*, i32** @ui_addr, align 4
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// CHECK-32B-NEXT: [[TMP2:%.*]] = bitcast i32* [[TMP1]] to i8*
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// CHECK-32B-NEXT: call void @llvm.ppc.store4r(i32 [[TMP0]], i8* [[TMP2]])
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// CHECK-32B-NEXT: ret void
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//
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void test_builtin_ppc_store4r() {
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__builtin_ppc_store4r(ui, ui_addr);
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}
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// CHECK-LABEL: @test_builtin_ppc_load2r(
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// CHECK: [[TMP0:%.*]] = load i16*, i16** @us_addr, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = bitcast i16* [[TMP0]] to i8*
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// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.load2r(i8* [[TMP1]])
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// CHECK-NEXT: [[CONV:%.*]] = trunc i32 [[TMP2]] to i16
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// CHECK-NEXT: ret i16 [[CONV]]
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//
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// CHECK-32B-LABEL: @test_builtin_ppc_load2r(
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// CHECK-32B: [[TMP0:%.*]] = load i16*, i16** @us_addr, align 4
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// CHECK-32B-NEXT: [[TMP1:%.*]] = bitcast i16* [[TMP0]] to i8*
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// CHECK-32B-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.load2r(i8* [[TMP1]])
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// CHECK-32B-NEXT: [[CONV:%.*]] = trunc i32 [[TMP2]] to i16
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// CHECK-32B-NEXT: ret i16 [[CONV]]
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//
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unsigned short test_builtin_ppc_load2r() {
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return __builtin_ppc_load2r(us_addr);
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}
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// CHECK-LABEL: @test_builtin_ppc_load4r(
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// CHECK: [[TMP0:%.*]] = load i32*, i32** @ui_addr, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8*
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// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.load4r(i8* [[TMP1]])
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// CHECK-NEXT: ret i32 [[TMP2]]
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//
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// CHECK-32B-LABEL: @test_builtin_ppc_load4r(
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// CHECK-32B: [[TMP0:%.*]] = load i32*, i32** @ui_addr, align 4
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// CHECK-32B-NEXT: [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8*
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// CHECK-32B-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.load4r(i8* [[TMP1]])
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// CHECK-32B-NEXT: ret i32 [[TMP2]]
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//
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unsigned int test_builtin_ppc_load4r() {
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return __builtin_ppc_load4r(ui_addr);
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}
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// REQUIRES: powerpc-registered-target.
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// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
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// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
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// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
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// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
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// RUN: %clang_cc1 -triple powerpc-unknown-aix \
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// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
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// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
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// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
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extern unsigned int ui;
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extern unsigned long long ull;
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// CHECK-LABEL: @test_builtin_ppc_poppar4(
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// CHECK: [[TMP0:%.*]] = load i32, i32* @ui, align 4
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @ui, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ctpop.i32(i32 [[TMP1]])
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// CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 1
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// CHECK-NEXT: ret i32 [[TMP3]]
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//
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int test_builtin_ppc_poppar4() {
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return __builtin_ppc_poppar4(ui);
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}
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// CHECK-LABEL: @test_builtin_ppc_poppar8(
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// CHECK: [[TMP0:%.*]] = load i64, i64* @ull, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* @ull, align 8
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// CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP1]])
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// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 1
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// CHECK-NEXT: [[CAST:%.*]] = trunc i64 [[TMP3]] to i32
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// CHECK-NEXT: ret i32 [[CAST]]
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//
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int test_builtin_ppc_poppar8() {
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return __builtin_ppc_poppar8(ull);
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}
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@ -1598,6 +1598,26 @@ let TargetPrefix = "ppc" in {
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def int_ppc_maddld
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: GCCBuiltin<"__builtin_ppc_maddld">,
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Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
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// load
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def int_ppc_load2r
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: GCCBuiltin<"__builtin_ppc_load2r">,
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Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
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def int_ppc_load4r
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: GCCBuiltin<"__builtin_ppc_load4r">,
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Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
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def int_ppc_load8r
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: GCCBuiltin<"__builtin_ppc_load8r">,
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Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
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// store
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def int_ppc_store2r
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: GCCBuiltin<"__builtin_ppc_store2r">,
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Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty], [IntrWriteMem]>;
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def int_ppc_store4r
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: GCCBuiltin<"__builtin_ppc_store4r">,
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Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty], [IntrWriteMem]>;
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def int_ppc_store8r
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: GCCBuiltin<"__builtin_ppc_store8r">,
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Intrinsic<[], [llvm_i64_ty, llvm_ptr_ty], [IntrWriteMem]>;
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}
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//===----------------------------------------------------------------------===//
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@ -1790,6 +1790,10 @@ def : Pat<(i64 (int_ppc_mulhd g8rc:$a, g8rc:$b)),
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(i64 (MULHD $a, $b))>;
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def : Pat<(i64 (int_ppc_mulhdu g8rc:$a, g8rc:$b)),
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(i64 (MULHDU $a, $b))>;
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def : Pat<(int_ppc_load8r ForceXForm:$ptr),
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(LDBRX ForceXForm:$ptr)>;
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def : Pat<(int_ppc_store8r g8rc:$a, ForceXForm:$ptr),
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(STDBRX g8rc:$a, ForceXForm:$ptr)>;
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}
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let Predicates = [IsISA3_0] in {
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@ -5274,6 +5274,16 @@ def : Pat<(i32 (int_ppc_mulhw gprc:$a, gprc:$b)),
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def : Pat<(i32 (int_ppc_mulhwu gprc:$a, gprc:$b)),
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(i32 (MULHWU $a, $b))>;
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def : Pat<(int_ppc_load2r ForceXForm:$ptr),
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(LHBRX ForceXForm:$ptr)>;
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def : Pat<(int_ppc_load4r ForceXForm:$ptr),
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(LWBRX ForceXForm:$ptr)>;
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def : Pat<(int_ppc_store2r gprc:$a, ForceXForm:$ptr),
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(STHBRX gprc:$a, ForceXForm:$ptr)>;
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def : Pat<(int_ppc_store4r gprc:$a, ForceXForm:$ptr),
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(STWBRX gprc:$a, ForceXForm:$ptr)>;
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// Fast 32-bit reverse bits algorithm:
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// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit):
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// n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xAAAAAAAA);
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@ -0,0 +1,37 @@
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s
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@ull = external global i64, align 8
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@ull_addr = external global i64*, align 8
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define dso_local void @test_builtin_ppc_store8r() {
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; CHECK-LABEL: test_builtin_ppc_store8r:
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; CHECK: stdbrx 3, 0, 4
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; CHECK-NEXT: blr
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;
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entry:
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%0 = load i64, i64* @ull, align 8
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%1 = load i64*, i64** @ull_addr, align 8
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%2 = bitcast i64* %1 to i8*
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call void @llvm.ppc.store8r(i64 %0, i8* %2)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.ppc.store8r(i64, i8*)
|
||||
|
||||
define dso_local i64 @test_builtin_ppc_load8r() {
|
||||
; CHECK-LABEL: test_builtin_ppc_load8r:
|
||||
; CHECK: ldbrx 3, 0, 3
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%0 = load i64*, i64** @ull_addr, align 8
|
||||
%1 = bitcast i64* %0 to i8*
|
||||
%2 = call i64 @llvm.ppc.load8r(i8* %1)
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
declare i64 @llvm.ppc.load8r(i8*)
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
|
||||
; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-64B
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
|
||||
; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
|
||||
; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32B
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
|
||||
; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
|
||||
|
||||
@us = external global i16, align 2
|
||||
@us_addr = external global i16*, align 8
|
||||
@ui = external global i32, align 4
|
||||
@ui_addr = external global i32*, align 8
|
||||
|
||||
define dso_local void @test_builtin_ppc_store2r() {
|
||||
; CHECK-64B-LABEL: test_builtin_ppc_store2r:
|
||||
; CHECK-64B: sthbrx 3, 0, 4
|
||||
; CHECK-64B-NEXT: blr
|
||||
|
||||
; CHECK-32B-LABEL: test_builtin_ppc_store2r:
|
||||
; CHECK-32B: sthbrx 3, 0, 4
|
||||
; CHECK-32B-NEXT: blr
|
||||
entry:
|
||||
%0 = load i16, i16* @us, align 2
|
||||
%conv = zext i16 %0 to i32
|
||||
%1 = load i16*, i16** @us_addr, align 8
|
||||
%2 = bitcast i16* %1 to i8*
|
||||
call void @llvm.ppc.store2r(i32 %conv, i8* %2)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.ppc.store2r(i32, i8*)
|
||||
|
||||
define dso_local void @test_builtin_ppc_store4r() {
|
||||
; CHECK-64B-LABEL: test_builtin_ppc_store4r:
|
||||
; CHECK-64B: stwbrx 3, 0, 4
|
||||
; CHECK-64B-NEXT: blr
|
||||
|
||||
; CHECK-32B-LABEL: test_builtin_ppc_store4r:
|
||||
; CHECK-32B: stwbrx 3, 0, 4
|
||||
; CHECK-32B-NEXT: blr
|
||||
entry:
|
||||
%0 = load i32, i32* @ui, align 4
|
||||
%1 = load i32*, i32** @ui_addr, align 8
|
||||
%2 = bitcast i32* %1 to i8*
|
||||
call void @llvm.ppc.store4r(i32 %0, i8* %2)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.ppc.store4r(i32, i8*)
|
||||
|
||||
define dso_local zeroext i16 @test_builtin_ppc_load2r() {
|
||||
; CHECK-64B-LABEL: test_builtin_ppc_load2r:
|
||||
; CHECK-64B: lhbrx 3, 0, 3
|
||||
; CHECK-64B-NEXT: clrldi 3, 3, 48
|
||||
; CHECK-64B-NEXT: blr
|
||||
|
||||
; CHECK-32B-LABEL: test_builtin_ppc_load2r:
|
||||
; CHECK-32B: lhbrx 3, 0, 3
|
||||
; CHECK-32B-NEXT: clrlwi 3, 3, 16
|
||||
; CHECK-32B-NEXT: blr
|
||||
entry:
|
||||
%0 = load i16*, i16** @us_addr, align 8
|
||||
%1 = bitcast i16* %0 to i8*
|
||||
%2 = call i32 @llvm.ppc.load2r(i8* %1)
|
||||
%conv = trunc i32 %2 to i16
|
||||
ret i16 %conv
|
||||
}
|
||||
|
||||
declare i32 @llvm.ppc.load2r(i8*)
|
||||
|
||||
define dso_local zeroext i32 @test_builtin_ppc_load4r() {
|
||||
; CHECK-64B-LABEL: test_builtin_ppc_load4r:
|
||||
; CHECK-64B: lwbrx 3, 0, 3
|
||||
; CHECK-64B-NEXT: blr
|
||||
|
||||
; CHECK-32B-LABEL: test_builtin_ppc_load4r:
|
||||
; CHECK-32B: lwbrx 3, 0, 3
|
||||
; CHECK-32B-NEXT: blr
|
||||
entry:
|
||||
%0 = load i32*, i32** @ui_addr, align 8
|
||||
%1 = bitcast i32* %0 to i8*
|
||||
%2 = call i32 @llvm.ppc.load4r(i8* %1)
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
declare i32 @llvm.ppc.load4r(i8*)
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
|
||||
; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-64B
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
|
||||
; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
|
||||
; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32B
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
|
||||
; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
|
||||
|
||||
@ui = external global i32, align 4
|
||||
@ull = external global i64, align 8
|
||||
|
||||
define dso_local signext i32 @test_builtin_ppc_poppar4() {
|
||||
; CHECK-32B-LABEL: test_builtin_ppc_poppar4:
|
||||
; CHECK-32B: popcntw 3, 3
|
||||
; CHECK-32B-NEXT: clrlwi 3, 3, 31
|
||||
; CHECK-32B-NEXT: blr
|
||||
; CHECK-64B-LABEL: test_builtin_ppc_poppar4:
|
||||
; CHECK-64B: popcntw 3, 3
|
||||
; CHECK-64B-NEXT: clrlwi 3, 3, 31
|
||||
; CHECK-64B-NEXT: blr
|
||||
entry:
|
||||
%0 = load i32, i32* @ui, align 4
|
||||
%1 = load i32, i32* @ui, align 4
|
||||
%2 = call i32 @llvm.ctpop.i32(i32 %1)
|
||||
%3 = and i32 %2, 1
|
||||
ret i32 %3
|
||||
}
|
||||
|
||||
declare i32 @llvm.ctpop.i32(i32)
|
||||
|
||||
define dso_local signext i32 @test_builtin_ppc_poppar8() {
|
||||
; CHECK-32B-LABEL: test_builtin_ppc_poppar8:
|
||||
; CHECK-32B: xor 3, 3, 4
|
||||
; CHECK-32B-NEXT: popcntw 3, 3
|
||||
; CHECK-32B-NEXT: clrlwi 3, 3, 31
|
||||
; CHECK-32B-NEXT: blr
|
||||
; CHECK-64B-LABEL: test_builtin_ppc_poppar8:
|
||||
; CHECK-64B: popcntd 3, 3
|
||||
; CHECK-64B-NEXT: clrldi 3, 3, 63
|
||||
; CHECK-64B-NEXT: blr
|
||||
entry:
|
||||
%0 = load i64, i64* @ull, align 8
|
||||
%1 = load i64, i64* @ull, align 8
|
||||
%2 = call i64 @llvm.ctpop.i64(i64 %1)
|
||||
%3 = and i64 %2, 1
|
||||
%cast = trunc i64 %3 to i32
|
||||
ret i32 %cast
|
||||
}
|
||||
|
||||
declare i64 @llvm.ctpop.i64(i64)
|
||||
Loading…
Reference in New Issue