parent
6db5887db5
commit
4d9cf68023
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@ -134,6 +134,22 @@ void PPC32RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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}
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}
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}
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}
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unsigned PPC32RegisterInfo::isLoadFromStackSlot(MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case PPC::LWZ:
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case PPC::LFD:
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if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
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MI->getOperand(2).isFrameIndex()) {
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FrameIndex = MI->getOperand(2).getFrameIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
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/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
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/// copy instructions, turning them into load/store instructions.
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/// copy instructions, turning them into load/store instructions.
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MachineInstr *PPC32RegisterInfo::foldMemoryOperand(MachineInstr *MI,
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MachineInstr *PPC32RegisterInfo::foldMemoryOperand(MachineInstr *MI,
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@ -40,6 +40,8 @@ public:
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unsigned DestReg, unsigned SrcReg,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const;
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const TargetRegisterClass *RC) const;
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unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
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/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
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/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
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/// copy instructions, turning them into load/store instructions.
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/// copy instructions, turning them into load/store instructions.
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virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
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virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
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