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Allow TargetLowering::getRegClassFor() to be called on illegal types. Also 

allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.

llvm-svn: 103854
This commit is contained in:
Evan Cheng 2010-05-15 02:18:07 +00:00
parent 749dc33dff
commit 4cad68eb34
4 changed files with 29 additions and 9 deletions
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4
llvm/include/llvm/Target/TargetLowering.h
View File

@ -155,8 +155,8 @@ public:
}
/// getRegClassFor - Return the register class that should be used for the
/// specified value type. This may only be called on legal types.
TargetRegisterClass *getRegClassFor(EVT VT) const {
/// specified value type.
virtual TargetRegisterClass *getRegClassFor(EVT VT) const {
assert(VT.isSimple() && "getRegClassFor called on illegal type!");
TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
assert(RC && "This value type is not natively supported!");

20
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -266,13 +266,6 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
addQRTypeForNEON(MVT::v4i32);
addQRTypeForNEON(MVT::v2i64);
// Map v4i64 to QQ registers but do not make the type legal for any
// operations. Similarly map v8i64 to QQQQ registers. v4i64 and v8i64 are
// only used for REG_SEQUENCE to load / store 4 to 8 consecutive
// D registers.
addRegisterClass(MVT::v4i64, ARM::QQPRRegisterClass);
addRegisterClass(MVT::v8i64, ARM::QQQQPRRegisterClass);
// v2f64 is legal so that QR subregs can be extracted as f64 elements, but
// neither Neon nor VFP support any arithmetic operations on it.
setOperationAction(ISD::FADD, MVT::v2f64, Expand);
@ -586,6 +579,19 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
}
}
/// getRegClassFor - Return the register class that should be used for the
/// specified value type.
TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
// Map v4i64 to QQ registers but do not make the type legal. Similarly map
// v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
// load / store 4 to 8 consecutive D registers.
if (VT == MVT::v4i64)
return ARM::QQPRRegisterClass;
else if (VT == MVT::v8i64)
return ARM::QQQQPRRegisterClass;
return TargetLowering::getRegClassFor(VT);
}
/// getFunctionAlignment - Return the Log2 alignment of this function.
unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 0 : 1;

4
llvm/lib/Target/ARM/ARMISelLowering.h
View File

@ -240,6 +240,10 @@ namespace llvm {
return Subtarget;
}
/// getRegClassFor - Return the register class that should be used for the
/// specified value type.
virtual TargetRegisterClass *getRegClassFor(EVT VT) const;
/// getFunctionAlignment - Return the Log2 alignment of this function.
virtual unsigned getFunctionAlignment(const Function *F) const;

10
llvm/test/CodeGen/ARM/2010-05-14-IllegalType.ll Normal file
View File

@ -0,0 +1,10 @@
; RUN: llc -march=thumb -mcpu=cortex-a8 -mtriple=thumbv7-eabi -float-abi=hard < %s | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
target triple = "thumbv7-apple-darwin10"
define <4 x i64> @f_4_i64(<4 x i64> %a, <4 x i64> %b) nounwind {
; CHECK: vadd.i64
%y = add <4 x i64> %a, %b
ret <4 x i64> %y
}