[AArch64]Extend merging narrow loads into a wider load
This change extends r251438 to handle more narrow load promotions including byte type, unscaled, and signed. For example, this change will convert : ldursh w1, [x0, #-2] ldurh w2, [x0, #-4] into ldur w2, [x0, #-4] asr w1, w2, #16 and w2, w2, #0xffff llvm-svn: 253577
This commit is contained in:
Jun Bum Lim
parent
89d7ff5de6
commit
4c35ccac91
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@ -161,6 +161,9 @@ static bool isUnscaledLdSt(unsigned Opc) {
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case AArch64::LDURXi:
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case AArch64::LDURSWi:
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case AArch64::LDURHHi:
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case AArch64::LDURBBi:
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case AArch64::LDURSBWi:
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case AArch64::LDURSHWi:
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return true;
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}
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}
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@ -169,16 +172,39 @@ static bool isUnscaledLdSt(MachineInstr *MI) {
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return isUnscaledLdSt(MI->getOpcode());
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}
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static unsigned getBitExtrOpcode(MachineInstr *MI) {
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switch (MI->getOpcode()) {
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default:
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llvm_unreachable("Unexpected opcode.");
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case AArch64::LDRBBui:
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case AArch64::LDURBBi:
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case AArch64::LDRHHui:
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case AArch64::LDURHHi:
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return AArch64::UBFMWri;
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case AArch64::LDRSBWui:
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case AArch64::LDURSBWi:
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case AArch64::LDRSHWui:
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case AArch64::LDURSHWi:
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return AArch64::SBFMWri;
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}
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}
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static bool isSmallTypeLdMerge(unsigned Opc) {
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switch (Opc) {
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default:
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return false;
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case AArch64::LDRHHui:
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case AArch64::LDURHHi:
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case AArch64::LDRBBui:
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case AArch64::LDURBBi:
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case AArch64::LDRSHWui:
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case AArch64::LDURSHWi:
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case AArch64::LDRSBWui:
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case AArch64::LDURSBWi:
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return true;
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// FIXME: Add other instructions (e.g, LDRBBui, LDURSHWi, LDRSHWui, etc.).
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}
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}
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static bool isSmallTypeLdMerge(MachineInstr *MI) {
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return isSmallTypeLdMerge(MI->getOpcode());
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}
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@ -189,10 +215,15 @@ static int getMemScale(MachineInstr *MI) {
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default:
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llvm_unreachable("Opcode has unknown scale!");
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case AArch64::LDRBBui:
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case AArch64::LDURBBi:
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case AArch64::LDRSBWui:
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case AArch64::LDURSBWi:
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case AArch64::STRBBui:
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return 1;
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case AArch64::LDRHHui:
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case AArch64::LDURHHi:
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case AArch64::LDRSHWui:
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case AArch64::LDURSHWi:
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case AArch64::STRHHui:
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return 2;
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case AArch64::LDRSui:
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@ -265,11 +296,21 @@ static unsigned getMatchingNonSExtOpcode(unsigned Opc,
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case AArch64::LDURSi:
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case AArch64::LDRHHui:
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case AArch64::LDURHHi:
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case AArch64::LDRBBui:
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case AArch64::LDURBBi:
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return Opc;
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case AArch64::LDRSWui:
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return AArch64::LDRWui;
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case AArch64::LDURSWi:
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return AArch64::LDURWi;
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case AArch64::LDRSBWui:
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return AArch64::LDRBBui;
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case AArch64::LDRSHWui:
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return AArch64::LDRHHui;
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case AArch64::LDURSBWi:
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return AArch64::LDURBBi;
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case AArch64::LDURSHWi:
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return AArch64::LDURHHi;
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}
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}
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@ -311,9 +352,17 @@ static unsigned getMatchingPairOpcode(unsigned Opc) {
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case AArch64::LDURSWi:
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return AArch64::LDPSWi;
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case AArch64::LDRHHui:
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case AArch64::LDRSHWui:
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return AArch64::LDRWui;
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case AArch64::LDURHHi:
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case AArch64::LDURSHWi:
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return AArch64::LDURWi;
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case AArch64::LDRBBui:
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case AArch64::LDRSBWui:
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return AArch64::LDRHHui;
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case AArch64::LDURBBi:
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case AArch64::LDURSBWi:
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return AArch64::LDURHHi;
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}
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}
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@ -535,16 +584,16 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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if (isSmallTypeLdMerge(Opc)) {
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// Change the scaled offset from small to large type.
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if (!IsUnscaled)
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if (!IsUnscaled) {
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assert(((OffsetImm & 1) == 0) && "Unexpected offset to merge");
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OffsetImm /= 2;
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}
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MachineInstr *RtNewDest = MergeForward ? I : Paired;
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// When merging small (< 32 bit) loads for big-endian targets, the order of
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// the component parts gets swapped.
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if (!Subtarget->isLittleEndian())
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std::swap(RtMI, Rt2MI);
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// Construct the new load instruction.
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// FIXME: currently we support only halfword unsigned load. We need to
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// handle byte type, signed, and store instructions as well.
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MachineInstr *NewMemMI, *BitExtMI1, *BitExtMI2;
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NewMemMI = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
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TII->get(NewOpc))
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@ -564,35 +613,61 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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DEBUG(dbgs() << " with instructions:\n ");
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DEBUG((NewMemMI)->print(dbgs()));
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int Width = getMemScale(I) == 1 ? 8 : 16;
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int LSBLow = 0;
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int LSBHigh = Width;
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int ImmsLow = LSBLow + Width - 1;
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int ImmsHigh = LSBHigh + Width - 1;
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MachineInstr *ExtDestMI = MergeForward ? Paired : I;
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if ((ExtDestMI == Rt2MI) == Subtarget->isLittleEndian()) {
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// Create the bitfield extract for high half.
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// Create the bitfield extract for high bits.
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BitExtMI1 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
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TII->get(AArch64::UBFMWri))
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TII->get(getBitExtrOpcode(Rt2MI)))
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.addOperand(getLdStRegOp(Rt2MI))
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.addReg(getLdStRegOp(RtNewDest).getReg())
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.addImm(16)
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.addImm(31);
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// Create the bitfield extract for low half.
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BitExtMI2 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
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TII->get(AArch64::ANDWri))
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.addOperand(getLdStRegOp(RtMI))
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.addReg(getLdStRegOp(RtNewDest).getReg())
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.addImm(15);
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.addImm(LSBHigh)
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.addImm(ImmsHigh);
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// Create the bitfield extract for low bits.
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if (RtMI->getOpcode() == getMatchingNonSExtOpcode(RtMI->getOpcode())) {
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// For unsigned, prefer to use AND for low bits.
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BitExtMI2 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
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TII->get(AArch64::ANDWri))
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.addOperand(getLdStRegOp(RtMI))
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.addReg(getLdStRegOp(RtNewDest).getReg())
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.addImm(ImmsLow);
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} else {
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BitExtMI2 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
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TII->get(getBitExtrOpcode(RtMI)))
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.addOperand(getLdStRegOp(RtMI))
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.addReg(getLdStRegOp(RtNewDest).getReg())
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.addImm(LSBLow)
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.addImm(ImmsLow);
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}
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} else {
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// Create the bitfield extract for low half.
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BitExtMI1 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
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TII->get(AArch64::ANDWri))
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.addOperand(getLdStRegOp(RtMI))
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.addReg(getLdStRegOp(RtNewDest).getReg())
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.addImm(15);
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// Create the bitfield extract for high half.
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// Create the bitfield extract for low bits.
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if (RtMI->getOpcode() == getMatchingNonSExtOpcode(RtMI->getOpcode())) {
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// For unsigned, prefer to use AND for low bits.
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BitExtMI1 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
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TII->get(AArch64::ANDWri))
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.addOperand(getLdStRegOp(RtMI))
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.addReg(getLdStRegOp(RtNewDest).getReg())
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.addImm(ImmsLow);
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} else {
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BitExtMI1 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
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TII->get(getBitExtrOpcode(RtMI)))
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.addOperand(getLdStRegOp(RtMI))
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.addReg(getLdStRegOp(RtNewDest).getReg())
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.addImm(LSBLow)
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.addImm(ImmsLow);
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}
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// Create the bitfield extract for high bits.
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BitExtMI2 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
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TII->get(AArch64::UBFMWri))
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TII->get(getBitExtrOpcode(Rt2MI)))
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.addOperand(getLdStRegOp(Rt2MI))
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.addReg(getLdStRegOp(RtNewDest).getReg())
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.addImm(16)
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.addImm(31);
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.addImm(LSBHigh)
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.addImm(ImmsHigh);
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}
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DEBUG(dbgs() << " ");
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DEBUG((BitExtMI1)->print(dbgs()));
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@ -1173,7 +1248,7 @@ bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
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bool enableNarrowLdOpt) {
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bool Modified = false;
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// Three tranformations to do here:
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// 1) Find halfword loads that can be merged into a single 32-bit word load
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// 1) Find narrow loads that can be converted into a single wider load
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// with bitfield extract instructions.
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// e.g.,
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// ldrh w0, [x2]
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@ -1206,9 +1281,15 @@ bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
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++MBBI;
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break;
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// Scaled instructions.
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case AArch64::LDRBBui:
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case AArch64::LDRHHui:
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case AArch64::LDRSBWui:
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case AArch64::LDRSHWui:
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// Unscaled instructions.
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case AArch64::LDURHHi: {
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case AArch64::LDURBBi:
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case AArch64::LDURHHi:
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case AArch64::LDURSBWi:
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case AArch64::LDURSHWi: {
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if (tryToMergeLdStInst(MBBI)) {
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Modified = true;
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break;
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@ -60,3 +60,259 @@ define i16 @Ldrh_4_merge(i16* nocapture readonly %P) {
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%add14 = sub nuw nsw i16 %add9, %l3
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ret i16 %add14
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}
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; CHECK-LABEL: Ldrsh_merge
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; CHECK: ldr [[NEW_DEST:w[0-9]+]]
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; CHECK-DAG: asr [[LO_PART:w[0-9]+]], [[NEW_DEST]], #16
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; CHECK-DAG: sxth [[HI_PART:w[0-9]+]], [[NEW_DEST]]
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; LE: sub {{w[0-9]+}}, [[LO_PART]], [[HI_PART]]
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; BE: sub {{w[0-9]+}}, [[HI_PART]], [[LO_PART]]
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define i32 @Ldrsh_merge(i16* %p) nounwind {
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%add.ptr0 = getelementptr inbounds i16, i16* %p, i64 4
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%tmp = load i16, i16* %add.ptr0
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%add.ptr = getelementptr inbounds i16, i16* %p, i64 5
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%tmp1 = load i16, i16* %add.ptr
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%sexttmp = sext i16 %tmp to i32
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%sexttmp1 = sext i16 %tmp1 to i32
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%add = sub nsw i32 %sexttmp1, %sexttmp
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ret i32 %add
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}
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; CHECK-LABEL: Ldrsh_zsext_merge
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; CHECK: ldr [[NEW_DEST:w[0-9]+]]
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; LE-DAG: and [[LO_PART:w[0-9]+]], [[NEW_DEST]], #0xffff
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; LE-DAG: asr [[HI_PART:w[0-9]+]], [[NEW_DEST]], #16
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; BE-DAG: sxth [[LO_PART:w[0-9]+]], [[NEW_DEST]]
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; BE-DAG: lsr [[HI_PART:w[0-9]+]], [[NEW_DEST]], #16
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; LE: sub {{w[0-9]+}}, [[LO_PART]], [[HI_PART]]
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; BE: sub {{w[0-9]+}}, [[HI_PART]], [[LO_PART]]
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define i32 @Ldrsh_zsext_merge(i16* %p) nounwind {
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%add.ptr0 = getelementptr inbounds i16, i16* %p, i64 4
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%tmp = load i16, i16* %add.ptr0
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%add.ptr = getelementptr inbounds i16, i16* %p, i64 5
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%tmp1 = load i16, i16* %add.ptr
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%sexttmp = zext i16 %tmp to i32
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%sexttmp1 = sext i16 %tmp1 to i32
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%add = sub nsw i32 %sexttmp, %sexttmp1
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ret i32 %add
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}
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; CHECK-LABEL: Ldrsh_szext_merge
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; CHECK: ldr [[NEW_DEST:w[0-9]+]]
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; LE-DAG: sxth [[LO_PART:w[0-9]+]], [[NEW_DEST]]
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; LE-DAG: lsr [[HI_PART:w[0-9]+]], [[NEW_DEST]], #16
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; BE-DAG: and [[LO_PART:w[0-9]+]], [[NEW_DEST]], #0xffff
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; BE-DAG: asr [[HI_PART:w[0-9]+]], [[NEW_DEST]], #16
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; LE: sub {{w[0-9]+}}, [[LO_PART]], [[HI_PART]]
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; BE: sub {{w[0-9]+}}, [[HI_PART]], [[LO_PART]]
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define i32 @Ldrsh_szext_merge(i16* %p) nounwind {
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%add.ptr0 = getelementptr inbounds i16, i16* %p, i64 4
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%tmp = load i16, i16* %add.ptr0
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%add.ptr = getelementptr inbounds i16, i16* %p, i64 5
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%tmp1 = load i16, i16* %add.ptr
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%sexttmp = sext i16 %tmp to i32
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%sexttmp1 = zext i16 %tmp1 to i32
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%add = sub nsw i32 %sexttmp, %sexttmp1
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ret i32 %add
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}
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; CHECK-LABEL: Ldrb_merge
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; CHECK: ldrh [[NEW_DEST:w[0-9]+]]
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; CHECK-DAG: and [[LO_PART:w[0-9]+]], [[NEW_DEST]], #0xff
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; CHECK-DAG: ubfx [[HI_PART:w[0-9]+]], [[NEW_DEST]], #8, #8
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; LE: sub {{w[0-9]+}}, [[LO_PART]], [[HI_PART]]
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; BE: sub {{w[0-9]+}}, [[HI_PART]], [[LO_PART]]
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define i32 @Ldrb_merge(i8* %p) nounwind {
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%add.ptr0 = getelementptr inbounds i8, i8* %p, i64 2
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%tmp = load i8, i8* %add.ptr0
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%add.ptr = getelementptr inbounds i8, i8* %p, i64 3
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%tmp1 = load i8, i8* %add.ptr
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%sexttmp = zext i8 %tmp to i32
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%sexttmp1 = zext i8 %tmp1 to i32
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%add = sub nsw i32 %sexttmp, %sexttmp1
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ret i32 %add
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}
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; CHECK-LABEL: Ldrsb_merge
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; CHECK: ldrh [[NEW_DEST:w[0-9]+]]
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; CHECK-DAG: sxtb [[LO_PART:w[0-9]+]], [[NEW_DEST]]
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; CHECK-DAG: sbfx [[HI_PART:w[0-9]+]], [[NEW_DEST]], #8, #8
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; LE: sub {{w[0-9]+}}, [[LO_PART]], [[HI_PART]]
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; BE: sub {{w[0-9]+}}, [[HI_PART]], [[LO_PART]]
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define i32 @Ldrsb_merge(i8* %p) nounwind {
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%add.ptr0 = getelementptr inbounds i8, i8* %p, i64 2
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%tmp = load i8, i8* %add.ptr0
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%add.ptr = getelementptr inbounds i8, i8* %p, i64 3
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%tmp1 = load i8, i8* %add.ptr
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%sexttmp = sext i8 %tmp to i32
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%sexttmp1 = sext i8 %tmp1 to i32
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%add = sub nsw i32 %sexttmp, %sexttmp1
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ret i32 %add
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}
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; CHECK-LABEL: Ldrsb_zsext_merge
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; CHECK: ldrh [[NEW_DEST:w[0-9]+]]
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; LE-DAG: and [[LO_PART:w[0-9]+]], [[NEW_DEST]], #0xff
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; LE-DAG: sbfx [[HI_PART:w[0-9]+]], [[NEW_DEST]], #8, #8
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; BE-DAG: sxtb [[LO_PART:w[0-9]+]], [[NEW_DEST]]
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; BE-DAG: ubfx [[HI_PART:w[0-9]+]], [[NEW_DEST]], #8, #8
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; LE: sub {{w[0-9]+}}, [[LO_PART]], [[HI_PART]]
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; BE: sub {{w[0-9]+}}, [[HI_PART]], [[LO_PART]]
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define i32 @Ldrsb_zsext_merge(i8* %p) nounwind {
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%add.ptr0 = getelementptr inbounds i8, i8* %p, i64 2
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%tmp = load i8, i8* %add.ptr0
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%add.ptr = getelementptr inbounds i8, i8* %p, i64 3
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%tmp1 = load i8, i8* %add.ptr
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%sexttmp = zext i8 %tmp to i32
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%sexttmp1 = sext i8 %tmp1 to i32
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%add = sub nsw i32 %sexttmp, %sexttmp1
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ret i32 %add
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}
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; CHECK-LABEL: Ldrsb_szext_merge
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; CHECK: ldrh [[NEW_DEST:w[0-9]+]]
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; LE-DAG: sxtb [[LO_PART:w[0-9]+]], [[NEW_DEST]]
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; LE-DAG: ubfx [[HI_PART:w[0-9]+]], [[NEW_DEST]], #8, #8
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; BE-DAG: and [[LO_PART:w[0-9]+]], [[NEW_DEST]], #0xff
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; BE-DAG: sbfx [[HI_PART:w[0-9]+]], [[NEW_DEST]], #8, #8
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; LE: sub {{w[0-9]+}}, [[LO_PART]], [[HI_PART]]
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; BE: sub {{w[0-9]+}}, [[HI_PART]], [[LO_PART]]
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define i32 @Ldrsb_szext_merge(i8* %p) nounwind {
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%add.ptr0 = getelementptr inbounds i8, i8* %p, i64 2
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||||
%tmp = load i8, i8* %add.ptr0
|
||||
%add.ptr = getelementptr inbounds i8, i8* %p, i64 3
|
||||
%tmp1 = load i8, i8* %add.ptr
|
||||
%sexttmp = sext i8 %tmp to i32
|
||||
%sexttmp1 = zext i8 %tmp1 to i32
|
||||
%add = sub nsw i32 %sexttmp, %sexttmp1
|
||||
ret i32 %add
|
||||
}
|
||||
|
||||
; CHECK-LABEL: Ldursh_merge
|
||||
; CHECK: ldur [[NEW_DEST:w[0-9]+]]
|
||||
; CHECK-DAG: asr [[LO_PART:w[0-9]+]], [[NEW_DEST]], #16
|
||||
; CHECK-DAG: sxth [[HI_PART:w[0-9]+]], [[NEW_DEST]]
|
||||
; LE: sub {{w[0-9]+}}, [[LO_PART]], [[HI_PART]]
|
||||
; BE: sub {{w[0-9]+}}, [[HI_PART]], [[LO_PART]]
|
||||
define i32 @Ldursh_merge(i16* %p) nounwind {
|
||||
%add.ptr0 = getelementptr inbounds i16, i16* %p, i64 -1
|
||||
%tmp = load i16, i16* %add.ptr0
|
||||
%add.ptr = getelementptr inbounds i16, i16* %p, i64 -2
|
||||
%tmp1 = load i16, i16* %add.ptr
|
||||
%sexttmp = sext i16 %tmp to i32
|
||||
%sexttmp1 = sext i16 %tmp1 to i32
|
||||
%add = sub nsw i32 %sexttmp, %sexttmp1
|
||||
ret i32 %add
|
||||
}
|
||||
|
||||
; CHECK-LABEL: Ldursh_zsext_merge
|
||||
; CHECK: ldur [[NEW_DEST:w[0-9]+]]
|
||||
; LE-DAG: lsr [[LO_PART:w[0-9]+]], [[NEW_DEST]], #16
|
||||
; LE-DAG: sxth [[HI_PART:w[0-9]+]], [[NEW_DEST]]
|
||||
; BE-DAG: asr [[LO_PART:w[0-9]+]], [[NEW_DEST]], #16
|
||||
; BE-DAG: and [[HI_PART:w[0-9]+]], [[NEW_DEST]], #0xffff
|
||||
; LE: sub {{w[0-9]+}}, [[LO_PART]], [[HI_PART]]
|
||||
; BE: sub {{w[0-9]+}}, [[HI_PART]], [[LO_PART]]
|
||||
define i32 @Ldursh_zsext_merge(i16* %p) nounwind {
|
||||
%add.ptr0 = getelementptr inbounds i16, i16* %p, i64 -1
|
||||
%tmp = load i16, i16* %add.ptr0
|
||||
%add.ptr = getelementptr inbounds i16, i16* %p, i64 -2
|
||||
%tmp1 = load i16, i16* %add.ptr
|
||||
%sexttmp = zext i16 %tmp to i32
|
||||
%sexttmp1 = sext i16 %tmp1 to i32
|
||||
%add = sub nsw i32 %sexttmp, %sexttmp1
|
||||
ret i32 %add
|
||||
}
|
||||
|
||||
; CHECK-LABEL: Ldursh_szext_merge
|
||||
; CHECK: ldur [[NEW_DEST:w[0-9]+]]
|
||||
; LE-DAG: asr [[LO_PART:w[0-9]+]], [[NEW_DEST]], #16
|
||||
; LE-DAG: and [[HI_PART:w[0-9]+]], [[NEW_DEST]], #0xffff
|
||||
; BE-DAG: lsr [[LO_PART:w[0-9]+]], [[NEW_DEST]], #16
|
||||
; BE-DAG: sxth [[HI_PART:w[0-9]+]], [[NEW_DEST]]
|
||||
; LE: sub {{w[0-9]+}}, [[LO_PART]], [[HI_PART]]
|
||||
; BE: sub {{w[0-9]+}}, [[HI_PART]], [[LO_PART]]
|
||||
define i32 @Ldursh_szext_merge(i16* %p) nounwind {
|
||||
%add.ptr0 = getelementptr inbounds i16, i16* %p, i64 -1
|
||||
%tmp = load i16, i16* %add.ptr0
|
||||
%add.ptr = getelementptr inbounds i16, i16* %p, i64 -2
|
||||
%tmp1 = load i16, i16* %add.ptr
|
||||
%sexttmp = sext i16 %tmp to i32
|
||||
%sexttmp1 = zext i16 %tmp1 to i32
|
||||
%add = sub nsw i32 %sexttmp, %sexttmp1
|
||||
ret i32 %add
|
||||
}
|
||||
|
||||
; CHECK-LABEL: Ldurb_merge
|
||||
; CHECK: ldurh [[NEW_DEST:w[0-9]+]]
|
||||
; CHECK-DAG: ubfx [[LO_PART:w[0-9]+]], [[NEW_DEST]], #8, #8
|
||||
; CHECK-DAG: and [[HI_PART:w[0-9]+]], [[NEW_DEST]], #0xff
|
||||
; LE: sub {{w[0-9]+}}, [[LO_PART]], [[HI_PART]]
|
||||
; BE: sub {{w[0-9]+}}, [[HI_PART]], [[LO_PART]]
|
||||
define i32 @Ldurb_merge(i8* %p) nounwind {
|
||||
%add.ptr0 = getelementptr inbounds i8, i8* %p, i64 -1
|
||||
%tmp = load i8, i8* %add.ptr0
|
||||
%add.ptr = getelementptr inbounds i8, i8* %p, i64 -2
|
||||
%tmp1 = load i8, i8* %add.ptr
|
||||
%sexttmp = zext i8 %tmp to i32
|
||||
%sexttmp1 = zext i8 %tmp1 to i32
|
||||
%add = sub nsw i32 %sexttmp, %sexttmp1
|
||||
ret i32 %add
|
||||
}
|
||||
|
||||
; CHECK-LABEL: Ldursb_merge
|
||||
; CHECK: ldurh [[NEW_DEST:w[0-9]+]]
|
||||
; CHECK-DAG: sbfx [[LO_PART:w[0-9]+]], [[NEW_DEST]], #8, #8
|
||||
; CHECK-DAG: sxtb [[HI_PART:w[0-9]+]], [[NEW_DEST]]
|
||||
; LE: sub {{w[0-9]+}}, [[LO_PART]], [[HI_PART]]
|
||||
; BE: sub {{w[0-9]+}}, [[HI_PART]], [[LO_PART]]
|
||||
define i32 @Ldursb_merge(i8* %p) nounwind {
|
||||
%add.ptr0 = getelementptr inbounds i8, i8* %p, i64 -1
|
||||
%tmp = load i8, i8* %add.ptr0
|
||||
%add.ptr = getelementptr inbounds i8, i8* %p, i64 -2
|
||||
%tmp1 = load i8, i8* %add.ptr
|
||||
%sexttmp = sext i8 %tmp to i32
|
||||
%sexttmp1 = sext i8 %tmp1 to i32
|
||||
%add = sub nsw i32 %sexttmp, %sexttmp1
|
||||
ret i32 %add
|
||||
}
|
||||
|
||||
; CHECK-LABEL: Ldursb_zsext_merge
|
||||
; CHECK: ldurh [[NEW_DEST:w[0-9]+]]
|
||||
; LE-DAG: ubfx [[LO_PART:w[0-9]+]], [[NEW_DEST]], #8, #8
|
||||
; LE-DAG: sxtb [[HI_PART:w[0-9]+]], [[NEW_DEST]]
|
||||
; BE-DAG: sbfx [[LO_PART:w[0-9]+]], [[NEW_DEST]], #8, #8
|
||||
; BE-DAG: and [[HI_PART:w[0-9]+]], [[NEW_DEST]], #0xff
|
||||
; LE: sub {{w[0-9]+}}, [[LO_PART]], [[HI_PART]]
|
||||
; BE: sub {{w[0-9]+}}, [[HI_PART]], [[LO_PART]]
|
||||
define i32 @Ldursb_zsext_merge(i8* %p) nounwind {
|
||||
%add.ptr0 = getelementptr inbounds i8, i8* %p, i64 -1
|
||||
%tmp = load i8, i8* %add.ptr0
|
||||
%add.ptr = getelementptr inbounds i8, i8* %p, i64 -2
|
||||
%tmp1 = load i8, i8* %add.ptr
|
||||
%sexttmp = zext i8 %tmp to i32
|
||||
%sexttmp1 = sext i8 %tmp1 to i32
|
||||
%add = sub nsw i32 %sexttmp, %sexttmp1
|
||||
ret i32 %add
|
||||
}
|
||||
|
||||
; CHECK-LABEL: Ldursb_szext_merge
|
||||
; CHECK: ldurh [[NEW_DEST:w[0-9]+]]
|
||||
; LE-DAG: sbfx [[LO_PART:w[0-9]+]], [[NEW_DEST]], #8, #8
|
||||
; LE-DAG: and [[HI_PART:w[0-9]+]], [[NEW_DEST]], #0xff
|
||||
; BE-DAG: ubfx [[LO_PART:w[0-9]+]], [[NEW_DEST]], #8, #8
|
||||
; BE-DAG: sxtb [[HI_PART:w[0-9]+]], [[NEW_DEST]]
|
||||
; LE: sub {{w[0-9]+}}, [[LO_PART]], [[HI_PART]]
|
||||
; BE: sub {{w[0-9]+}}, [[HI_PART]], [[LO_PART]]
|
||||
define i32 @Ldursb_szext_merge(i8* %p) nounwind {
|
||||
%add.ptr0 = getelementptr inbounds i8, i8* %p, i64 -1
|
||||
%tmp = load i8, i8* %add.ptr0
|
||||
%add.ptr = getelementptr inbounds i8, i8* %p, i64 -2
|
||||
%tmp1 = load i8, i8* %add.ptr
|
||||
%sexttmp = sext i8 %tmp to i32
|
||||
%sexttmp1 = zext i8 %tmp1 to i32
|
||||
%add = sub nsw i32 %sexttmp, %sexttmp1
|
||||
ret i32 %add
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue