[PowerPC] Remove self-copies in pre-emit peephole
There are occasionally instances where AADB rewrites registers in such a way that a reg-reg copy becomes a self-copy. Such an instruction is obviously redundant and can be removed. This patch does precisely that. Note that this will not remove various nop's that we insert (which are themselves just self-copies). The reason those are left alone is that all of them have their own opcodes (that just encode to a self-copy). What prompted this patch is the fact that these self-copies sometimes end up using registers that make the instruction a priority-setting nop, thereby having a significant effect on performance. Differential revision: https://reviews.llvm.org/D52432 llvm-svn: 344036
This commit is contained in:
Nemanja Ivanovic
parent
a4be178def
commit
4c0b110e3e
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@ -192,6 +192,16 @@ public:
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bool isXFormMemOp(unsigned Opcode) const {
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return get(Opcode).TSFlags & PPCII::XFormMemOp;
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}
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static bool isSameClassPhysRegCopy(unsigned Opcode) {
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unsigned CopyOpcodes[] =
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{ PPC::OR, PPC::OR8, PPC::FMR, PPC::VOR, PPC::XXLOR, PPC::XXLORf,
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PPC::XSCPSGNDP, PPC::MCRF, PPC::QVFMR, PPC::QVFMRs, PPC::QVFMRb,
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PPC::CROR, PPC::EVOR, -1U };
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for (int i = 0; CopyOpcodes[i] != -1U; i++)
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if (Opcode == CopyOpcodes[i])
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return true;
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return false;
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}
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ScheduleHazardRecognizer *
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CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
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@ -34,6 +34,8 @@ STATISTIC(NumRRConvertedInPreEmit,
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"Number of r+r instructions converted to r+i in pre-emit peephole");
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STATISTIC(NumRemovedInPreEmit,
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"Number of instructions deleted in pre-emit peephole");
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STATISTIC(NumberOfSelfCopies,
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"Number of self copy instructions eliminated");
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static cl::opt<bool>
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RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(true),
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@ -65,6 +67,28 @@ namespace {
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SmallVector<MachineInstr *, 4> InstrsToErase;
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB) {
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unsigned Opc = MI.getOpcode();
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// Detect self copies - these can result from running AADB.
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if (PPCInstrInfo::isSameClassPhysRegCopy(Opc)) {
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const MCInstrDesc &MCID = TII->get(Opc);
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if (MCID.getNumOperands() == 3 &&
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MI.getOperand(0).getReg() == MI.getOperand(1).getReg() &&
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MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) {
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NumberOfSelfCopies++;
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LLVM_DEBUG(dbgs() << "Deleting self-copy instruction: ");
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LLVM_DEBUG(MI.dump());
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InstrsToErase.push_back(&MI);
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continue;
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}
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else if (MCID.getNumOperands() == 2 &&
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MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
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NumberOfSelfCopies++;
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LLVM_DEBUG(dbgs() << "Deleting self-copy instruction: ");
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LLVM_DEBUG(MI.dump());
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InstrsToErase.push_back(&MI);
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continue;
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}
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}
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MachineInstr *DefMIToErase = nullptr;
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if (TII->convertToImmediateForm(MI, &DefMIToErase)) {
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Changed = true;
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@ -0,0 +1,128 @@
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# RUN: llc -start-before ppc-pre-emit-peephole \
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# RUN: -verify-machineinstrs -ppc-asm-full-reg-names %s -o - | FileCheck %s
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--- |
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; ModuleID = 't.ll'
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source_filename = "t.ll"
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target datalayout = "e-m:e-i64:64-n32:64"
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define signext i32 @test(i32 signext %a, i32 signext %b, i32 signext %c) {
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entry:
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%cmp = icmp slt i32 %a, %b
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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%cmp1 = icmp slt i32 %b, %a
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br i1 %cmp1, label %return, label %if.end3
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if.end3: ; preds = %if.end
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%cmp4 = icmp eq i32 %a, %c
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br i1 %cmp4, label %if.then5, label %if.end6
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if.then5: ; preds = %if.end3
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%add = shl nsw i32 %a, 1
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br label %return
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if.end6: ; preds = %if.end3
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%cmp7 = icmp sgt i32 %c, %b
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%add11 = add i32 %c, %b
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%add12 = select i1 %cmp7, i32 %a, i32 0
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%spec.select = add i32 %add11, %add12
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ret i32 %spec.select
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return: ; preds = %if.then5, %if.end, %entry
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%retval.0 = phi i32 [ %add, %if.then5 ], [ %c, %entry ], [ %b, %if.end ]
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ret i32 %retval.0
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}
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...
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---
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name: test
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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registers:
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liveins:
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- { reg: '$x3', virtual-reg: '' }
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- { reg: '$x4', virtual-reg: '' }
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- { reg: '$x5', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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successors: %bb.4(0x40000000), %bb.1(0x40000000)
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liveins: $x3, $x4, $x5
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renamable $cr0 = CMPW renamable $r3, renamable $r4
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BCC 12, renamable $cr0, %bb.4
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bb.1.if.end:
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successors: %bb.6(0x40000000), %bb.2(0x40000000)
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liveins: $cr0, $x3, $x4, $x5
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BCC 36, killed renamable $cr0, %bb.2
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bb.6:
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liveins: $x4
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; CHECK: mr r5, r4
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; CHECK-NOT: mr r5, r5
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; CHECK: extsw r3, r5
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$r5 = OR killed $r4, $r4, implicit $x4, implicit-def $x5
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$r5 = OR $r5, $r5, implicit-def $x5
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renamable $x3 = EXTSW_32_64 killed renamable $r5, implicit $x5
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BLR8 implicit $lr8, implicit $rm, implicit killed $x3
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bb.2.if.end3:
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successors: %bb.3(0x40000000), %bb.5(0x40000000)
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liveins: $x3, $x4, $x5
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renamable $cr0 = CMPLW renamable $r3, renamable $r5
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BCC 68, killed renamable $cr0, %bb.5
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bb.3.if.then5:
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successors: %bb.4(0x80000000)
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liveins: $x3
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renamable $r5 = RLWINM killed renamable $r3, 1, 0, 30, implicit $x3, implicit-def $x5
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bb.4.return:
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liveins: $x5
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renamable $x3 = EXTSW_32_64 killed renamable $r5, implicit $x5
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BLR8 implicit $lr8, implicit $rm, implicit killed $x3
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bb.5.if.end6:
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liveins: $x3, $x4, $x5
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renamable $cr0 = CMPW renamable $r5, renamable $r4
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renamable $r6 = LI 0
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renamable $r4 = ADD4 killed renamable $r5, killed renamable $r4, implicit $x4, implicit $x5
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renamable $r3 = ISEL killed renamable $r3, killed renamable $r6, killed renamable $cr0gt, implicit $cr0, implicit $x3
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renamable $r3 = ADD4 killed renamable $r4, killed renamable $r3
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renamable $x3 = EXTSW_32_64 killed renamable $r3
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BLR8 implicit $lr8, implicit $rm, implicit killed $x3
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...
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