parent
457367f14c
commit
4bfb4a215d
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@ -199,6 +199,25 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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break;
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break;
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}
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}
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}
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}
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case ISD::SIGN_EXTEND_INREG:
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switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
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default: assert(0 && "Illegal type in SIGN_EXTEND_INREG"); break;
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case MVT::i16:
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::EXTSH, Select(N->getOperand(0)));
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break;
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case MVT::i8:
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::EXTSB, Select(N->getOperand(0)));
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break;
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case MVT::i1:
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::SUBFIC, Select(N->getOperand(0)),
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getI32Imm(0));
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break;
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}
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break;
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case ISD::CTLZ:
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assert(N->getValueType(0) == MVT::i32);
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::CNTLZW, Select(N->getOperand(0)));
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break;
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case ISD::ADD: {
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case ISD::ADD: {
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MVT::ValueType Ty = N->getValueType(0);
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MVT::ValueType Ty = N->getValueType(0);
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if (Ty == MVT::i32) {
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if (Ty == MVT::i32) {
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@ -298,23 +317,30 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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Select(N->getOperand(1)));
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Select(N->getOperand(1)));
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break;
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break;
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}
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}
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case ISD::MULHS: {
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case ISD::MULHS:
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assert(N->getValueType(0) == MVT::i32);
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assert(N->getValueType(0) == MVT::i32);
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CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::MULHW,
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::MULHW, Select(N->getOperand(0)),
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Select(N->getOperand(0)), Select(N->getOperand(1)));
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Select(N->getOperand(1)));
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break;
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break;
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}
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case ISD::MULHU:
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case ISD::MULHU: {
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assert(N->getValueType(0) == MVT::i32);
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assert(N->getValueType(0) == MVT::i32);
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CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::MULHWU,
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::MULHWU, Select(N->getOperand(0)),
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Select(N->getOperand(0)), Select(N->getOperand(1)));
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Select(N->getOperand(1)));
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break;
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break;
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}
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case ISD::FABS:
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case ISD::FABS: {
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CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::FABS,
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CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::FABS,
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Select(N->getOperand(0)));
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Select(N->getOperand(0)));
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break;
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break;
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}
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case ISD::FP_EXTEND:
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assert(MVT::f64 == N->getValueType(0) &&
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MVT::f32 == N->getOperand(0).getValueType() && "Illegal FP_EXTEND");
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CurDAG->SelectNodeTo(N, MVT::f64, PPC::FMR, Select(N->getOperand(0)));
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break;
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case ISD::FP_ROUND:
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assert(MVT::f32 == N->getValueType(0) &&
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MVT::f64 == N->getOperand(0).getValueType() && "Illegal FP_ROUND");
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CurDAG->SelectNodeTo(N, MVT::f32, PPC::FRSP, Select(N->getOperand(0)));
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break;
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case ISD::FNEG: {
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case ISD::FNEG: {
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SDOperand Val = Select(N->getOperand(0));
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SDOperand Val = Select(N->getOperand(0));
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MVT::ValueType Ty = N->getValueType(0);
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MVT::ValueType Ty = N->getValueType(0);
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