revert r196152.
This is a duplicate implementation. E.g. this patch defines: float64_t vabd_f64(float64_t a, float64_t b) But there is already a similar intrinsic "vabdd_f64" with the same types. Also, this intrinsic will be conflicted to the vector type intrinsic as following(Which is implemented by me and will be committed to trunk): float64x1_t vabd_f64(float64x1_t a, float64x1_t b). Two functions shouldn't have a same name in arm_neon.h. According to ARM ACLE document, such vabd_f64 with float64_t is not existing. So I revert this commit. llvm-svn: 196205
This commit is contained in:
parent
bbbf50541b
commit
4b850c5e0d
|
@ -228,7 +228,6 @@ class NoTestOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {}
|
|||
|
||||
// size modifiers:
|
||||
// S: scalar, only used for function mangling.
|
||||
// T: scalar, but without the BHSD suffix mangling.
|
||||
// U: unsigned
|
||||
// Q: 128b
|
||||
// H: 128b without mangling 'q'
|
||||
|
@ -1140,36 +1139,36 @@ def SCALAR_FRSQRTS : IInst<"vrsqrts", "sss", "SfSd">;
|
|||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Scalar Signed Integer Convert To Floating-point
|
||||
def SCALAR_SCVTFS : SInst<"vcvt_f32", "ys", "Si">;
|
||||
def SCALAR_SCVTFD : SInst<"vcvt_f64", "os", "SlTl">;
|
||||
def SCALAR_SCVTFD : SInst<"vcvt_f64", "os", "Sl">;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Scalar Unsigned Integer Convert To Floating-point
|
||||
def SCALAR_UCVTFS : SInst<"vcvt_f32", "ys", "SUi">;
|
||||
def SCALAR_UCVTFD : SInst<"vcvt_f64", "os", "SUlTUl">;
|
||||
def SCALAR_UCVTFD : SInst<"vcvt_f64", "os", "SUl">;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Scalar Floating-point Converts
|
||||
def SCALAR_FCVTXN : IInst<"vcvtx_f32", "ys", "Sd">;
|
||||
def SCALAR_FCVTNSS : SInst<"vcvtn_s32", "$s", "Sf">;
|
||||
def SCALAR_FCVTNUS : SInst<"vcvtn_u32", "bs", "Sf">;
|
||||
def SCALAR_FCVTNSD : SInst<"vcvtn_s64", "$s", "SdTd">;
|
||||
def SCALAR_FCVTNUD : SInst<"vcvtn_u64", "bs", "SdTd">;
|
||||
def SCALAR_FCVTNSD : SInst<"vcvtn_s64", "$s", "Sd">;
|
||||
def SCALAR_FCVTNUD : SInst<"vcvtn_u64", "bs", "Sd">;
|
||||
def SCALAR_FCVTMSS : SInst<"vcvtm_s32", "$s", "Sf">;
|
||||
def SCALAR_FCVTMUS : SInst<"vcvtm_u32", "bs", "Sf">;
|
||||
def SCALAR_FCVTMSD : SInst<"vcvtm_s64", "$s", "SdTd">;
|
||||
def SCALAR_FCVTMUD : SInst<"vcvtm_u64", "bs", "SdTd">;
|
||||
def SCALAR_FCVTMSD : SInst<"vcvtm_s64", "$s", "Sd">;
|
||||
def SCALAR_FCVTMUD : SInst<"vcvtm_u64", "bs", "Sd">;
|
||||
def SCALAR_FCVTASS : SInst<"vcvta_s32", "$s", "Sf">;
|
||||
def SCALAR_FCVTAUS : SInst<"vcvta_u32", "bs", "Sf">;
|
||||
def SCALAR_FCVTASD : SInst<"vcvta_s64", "$s", "SdTd">;
|
||||
def SCALAR_FCVTAUD : SInst<"vcvta_u64", "bs", "SdTd">;
|
||||
def SCALAR_FCVTASD : SInst<"vcvta_s64", "$s", "Sd">;
|
||||
def SCALAR_FCVTAUD : SInst<"vcvta_u64", "bs", "Sd">;
|
||||
def SCALAR_FCVTPSS : SInst<"vcvtp_s32", "$s", "Sf">;
|
||||
def SCALAR_FCVTPUS : SInst<"vcvtp_u32", "bs", "Sf">;
|
||||
def SCALAR_FCVTPSD : SInst<"vcvtp_s64", "$s", "SdTd">;
|
||||
def SCALAR_FCVTPUD : SInst<"vcvtp_u64", "bs", "SdTd">;
|
||||
def SCALAR_FCVTPSD : SInst<"vcvtp_s64", "$s", "Sd">;
|
||||
def SCALAR_FCVTPUD : SInst<"vcvtp_u64", "bs", "Sd">;
|
||||
def SCALAR_FCVTZSS : SInst<"vcvt_s32", "$s", "Sf">;
|
||||
def SCALAR_FCVTZUS : SInst<"vcvt_u32", "bs", "Sf">;
|
||||
def SCALAR_FCVTZSD : SInst<"vcvt_s64", "$s", "SdTd">;
|
||||
def SCALAR_FCVTZUD : SInst<"vcvt_u64", "bs", "SdTd">;
|
||||
def SCALAR_FCVTZSD : SInst<"vcvt_s64", "$s", "Sd">;
|
||||
def SCALAR_FCVTZUD : SInst<"vcvt_u64", "bs", "Sd">;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Scalar Floating-point Reciprocal Estimate
|
||||
|
@ -1228,7 +1227,7 @@ def SCALAR_ABS : SInst<"vabs", "ss", "Sl">;
|
|||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Scalar Absolute Difference
|
||||
def SCALAR_ABD : IInst<"vabd", "sss", "SfSdTd">;
|
||||
def SCALAR_ABD : IInst<"vabd", "sss", "SfSd">;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Scalar Signed Saturating Absolute Value
|
||||
|
|
|
@ -2126,7 +2126,6 @@ static Value *EmitAArch64ScalarBuiltinExpr(CodeGenFunction &CGF,
|
|||
case AArch64::BI__builtin_neon_vcvts_f32_s32:
|
||||
Int = Intrinsic::aarch64_neon_vcvtf32_s32,
|
||||
s = "vcvtf"; OverloadInt = false; break;
|
||||
case AArch64::BI__builtin_neon_vcvt_f64_s64:
|
||||
case AArch64::BI__builtin_neon_vcvtd_f64_s64:
|
||||
Int = Intrinsic::aarch64_neon_vcvtf64_s64,
|
||||
s = "vcvtf"; OverloadInt = false; break;
|
||||
|
@ -2134,7 +2133,6 @@ static Value *EmitAArch64ScalarBuiltinExpr(CodeGenFunction &CGF,
|
|||
case AArch64::BI__builtin_neon_vcvts_f32_u32:
|
||||
Int = Intrinsic::aarch64_neon_vcvtf32_u32,
|
||||
s = "vcvtf"; OverloadInt = false; break;
|
||||
case AArch64::BI__builtin_neon_vcvt_f64_u64:
|
||||
case AArch64::BI__builtin_neon_vcvtd_f64_u64:
|
||||
Int = Intrinsic::aarch64_neon_vcvtf64_u64,
|
||||
s = "vcvtf"; OverloadInt = false; break;
|
||||
|
@ -2144,52 +2142,42 @@ static Value *EmitAArch64ScalarBuiltinExpr(CodeGenFunction &CGF,
|
|||
s = "vcvtxn"; OverloadCvtInt = true; break;
|
||||
case AArch64::BI__builtin_neon_vcvtas_s32_f32:
|
||||
case AArch64::BI__builtin_neon_vcvtad_s64_f64:
|
||||
case AArch64::BI__builtin_neon_vcvta_s64_f64:
|
||||
Int = Intrinsic::aarch64_neon_fcvtas;
|
||||
s = "vcvtas"; OverloadCvtInt = true; break;
|
||||
case AArch64::BI__builtin_neon_vcvtas_u32_f32:
|
||||
case AArch64::BI__builtin_neon_vcvtad_u64_f64:
|
||||
case AArch64::BI__builtin_neon_vcvta_u64_f64:
|
||||
Int = Intrinsic::aarch64_neon_fcvtau;
|
||||
s = "vcvtau"; OverloadCvtInt = true; break;
|
||||
case AArch64::BI__builtin_neon_vcvtms_s32_f32:
|
||||
case AArch64::BI__builtin_neon_vcvtmd_s64_f64:
|
||||
case AArch64::BI__builtin_neon_vcvtm_s64_f64:
|
||||
Int = Intrinsic::aarch64_neon_fcvtms;
|
||||
s = "vcvtms"; OverloadCvtInt = true; break;
|
||||
case AArch64::BI__builtin_neon_vcvtms_u32_f32:
|
||||
case AArch64::BI__builtin_neon_vcvtmd_u64_f64:
|
||||
case AArch64::BI__builtin_neon_vcvtm_u64_f64:
|
||||
Int = Intrinsic::aarch64_neon_fcvtmu;
|
||||
s = "vcvtmu"; OverloadCvtInt = true; break;
|
||||
case AArch64::BI__builtin_neon_vcvtns_s32_f32:
|
||||
case AArch64::BI__builtin_neon_vcvtnd_s64_f64:
|
||||
case AArch64::BI__builtin_neon_vcvtn_s64_f64:
|
||||
Int = Intrinsic::aarch64_neon_fcvtns;
|
||||
s = "vcvtns"; OverloadCvtInt = true; break;
|
||||
case AArch64::BI__builtin_neon_vcvtns_u32_f32:
|
||||
case AArch64::BI__builtin_neon_vcvtnd_u64_f64:
|
||||
case AArch64::BI__builtin_neon_vcvtn_u64_f64:
|
||||
Int = Intrinsic::aarch64_neon_fcvtnu;
|
||||
s = "vcvtnu"; OverloadCvtInt = true; break;
|
||||
case AArch64::BI__builtin_neon_vcvtps_s32_f32:
|
||||
case AArch64::BI__builtin_neon_vcvtpd_s64_f64:
|
||||
case AArch64::BI__builtin_neon_vcvtp_s64_f64:
|
||||
Int = Intrinsic::aarch64_neon_fcvtps;
|
||||
s = "vcvtps"; OverloadCvtInt = true; break;
|
||||
case AArch64::BI__builtin_neon_vcvtps_u32_f32:
|
||||
case AArch64::BI__builtin_neon_vcvtpd_u64_f64:
|
||||
case AArch64::BI__builtin_neon_vcvtp_u64_f64:
|
||||
Int = Intrinsic::aarch64_neon_fcvtpu;
|
||||
s = "vcvtpu"; OverloadCvtInt = true; break;
|
||||
case AArch64::BI__builtin_neon_vcvts_s32_f32:
|
||||
case AArch64::BI__builtin_neon_vcvtd_s64_f64:
|
||||
case AArch64::BI__builtin_neon_vcvt_s64_f64:
|
||||
Int = Intrinsic::aarch64_neon_fcvtzs;
|
||||
s = "vcvtzs"; OverloadCvtInt = true; break;
|
||||
case AArch64::BI__builtin_neon_vcvts_u32_f32:
|
||||
case AArch64::BI__builtin_neon_vcvtd_u64_f64:
|
||||
case AArch64::BI__builtin_neon_vcvt_u64_f64:
|
||||
Int = Intrinsic::aarch64_neon_fcvtzu;
|
||||
s = "vcvtzu"; OverloadCvtInt = true; break;
|
||||
// Scalar Floating-point Reciprocal Estimate
|
||||
|
@ -2362,7 +2350,6 @@ static Value *EmitAArch64ScalarBuiltinExpr(CodeGenFunction &CGF,
|
|||
s = "vabs"; OverloadInt = false; break;
|
||||
// Scalar Absolute Difference
|
||||
case AArch64::BI__builtin_neon_vabds_f32:
|
||||
case AArch64::BI__builtin_neon_vabd_f64:
|
||||
case AArch64::BI__builtin_neon_vabdd_f64:
|
||||
Int = Intrinsic::aarch64_neon_vabd;
|
||||
s = "vabd"; OverloadInt = true; break;
|
||||
|
|
|
@ -18,18 +18,12 @@ int32_t test_vcvtas_s32_f32(float32_t a) {
|
|||
return (int32_t)vcvtas_s32_f32(a);
|
||||
}
|
||||
|
||||
int64_t test_vcvtad_s64_f64(float64_t a) {
|
||||
// CHECK: test_vcvtad_s64_f64
|
||||
int64_t test_test_vcvtad_s64_f64(float64_t a) {
|
||||
// CHECK: test_test_vcvtad_s64_f64
|
||||
// CHECK: fcvtas {{d[0-9]+}}, {{d[0-9]+}}
|
||||
return (int64_t)vcvtad_s64_f64(a);
|
||||
}
|
||||
|
||||
int64_t test_vcvta_s64_f64(float64_t a) {
|
||||
// CHECK: test_vcvta_s64_f64
|
||||
// CHECK: fcvtas {{d[0-9]+}}, {{d[0-9]+}}
|
||||
return (int64_t)vcvta_s64_f64(a);
|
||||
}
|
||||
|
||||
uint32_t test_vcvtas_u32_f32(float32_t a) {
|
||||
// CHECK: test_vcvtas_u32_f32
|
||||
// CHECK: fcvtau {{s[0-9]+}}, {{s[0-9]+}}
|
||||
|
@ -42,12 +36,6 @@ uint64_t test_vcvtad_u64_f64(float64_t a) {
|
|||
return (uint64_t)vcvtad_u64_f64(a);
|
||||
}
|
||||
|
||||
uint64_t test_vcvta_u64_f64(float64_t a) {
|
||||
// CHECK: test_vcvta_u64_f64
|
||||
// CHECK: fcvtau {{d[0-9]+}}, {{d[0-9]+}}
|
||||
return (uint64_t)vcvta_u64_f64(a);
|
||||
}
|
||||
|
||||
int32_t test_vcvtms_s32_f32(float32_t a) {
|
||||
// CHECK: test_vcvtms_s32_f32
|
||||
// CHECK: fcvtms {{s[0-9]+}}, {{s[0-9]+}}
|
||||
|
@ -60,12 +48,6 @@ int64_t test_vcvtmd_s64_f64(float64_t a) {
|
|||
return (int64_t)vcvtmd_s64_f64(a);
|
||||
}
|
||||
|
||||
int64_t test_vcvtm_s64_f64(float64_t a) {
|
||||
// CHECK: test_vcvtm_s64_f64
|
||||
// CHECK: fcvtms {{d[0-9]+}}, {{d[0-9]+}}
|
||||
return (int64_t)vcvtm_s64_f64(a);
|
||||
}
|
||||
|
||||
uint32_t test_vcvtms_u32_f32(float32_t a) {
|
||||
// CHECK: test_vcvtms_u32_f32
|
||||
// CHECK: fcvtmu {{s[0-9]+}}, {{s[0-9]+}}
|
||||
|
@ -78,12 +60,6 @@ uint64_t test_vcvtmd_u64_f64(float64_t a) {
|
|||
return (uint64_t)vcvtmd_u64_f64(a);
|
||||
}
|
||||
|
||||
uint64_t test_vcvtm_u64_f64(float64_t a) {
|
||||
// CHECK: test_vcvtm_u64_f64
|
||||
// CHECK: fcvtmu {{d[0-9]+}}, {{d[0-9]+}}
|
||||
return (uint64_t)vcvtm_u64_f64(a);
|
||||
}
|
||||
|
||||
int32_t test_vcvtns_s32_f32(float32_t a) {
|
||||
// CHECK: test_vcvtns_s32_f32
|
||||
// CHECK: fcvtns {{s[0-9]+}}, {{s[0-9]+}}
|
||||
|
@ -96,12 +72,6 @@ int64_t test_vcvtnd_s64_f64(float64_t a) {
|
|||
return (int64_t)vcvtnd_s64_f64(a);
|
||||
}
|
||||
|
||||
int64_t test_vcvtn_s64_f64(float64_t a) {
|
||||
// CHECK: test_vcvtn_s64_f64
|
||||
// CHECK: fcvtns {{d[0-9]+}}, {{d[0-9]+}}
|
||||
return (int64_t)vcvtn_s64_f64(a);
|
||||
}
|
||||
|
||||
uint32_t test_vcvtns_u32_f32(float32_t a) {
|
||||
// CHECK: test_vcvtns_u32_f32
|
||||
// CHECK: fcvtnu {{s[0-9]+}}, {{s[0-9]+}}
|
||||
|
@ -114,12 +84,6 @@ uint64_t test_vcvtnd_u64_f64(float64_t a) {
|
|||
return (uint64_t)vcvtnd_u64_f64(a);
|
||||
}
|
||||
|
||||
uint64_t test_vcvtn_u64_f64(float64_t a) {
|
||||
// CHECK: test_vcvtn_u64_f64
|
||||
// CHECK: fcvtnu {{d[0-9]+}}, {{d[0-9]+}}
|
||||
return (uint64_t)vcvtn_u64_f64(a);
|
||||
}
|
||||
|
||||
int32_t test_vcvtps_s32_f32(float32_t a) {
|
||||
// CHECK: test_vcvtps_s32_f32
|
||||
// CHECK: fcvtps {{s[0-9]+}}, {{s[0-9]+}}
|
||||
|
@ -132,12 +96,6 @@ int64_t test_vcvtpd_s64_f64(float64_t a) {
|
|||
return (int64_t)vcvtpd_s64_f64(a);
|
||||
}
|
||||
|
||||
int64_t test_vcvtp_s64_f64(float64_t a) {
|
||||
// CHECK: test_vcvtp_s64_f64
|
||||
// CHECK: fcvtps {{d[0-9]+}}, {{d[0-9]+}}
|
||||
return (int64_t)vcvtp_s64_f64(a);
|
||||
}
|
||||
|
||||
uint32_t test_vcvtps_u32_f32(float32_t a) {
|
||||
// CHECK: test_vcvtps_u32_f32
|
||||
// CHECK: fcvtpu {{s[0-9]+}}, {{s[0-9]+}}
|
||||
|
@ -150,12 +108,6 @@ uint64_t test_vcvtpd_u64_f64(float64_t a) {
|
|||
return (uint64_t)vcvtpd_u64_f64(a);
|
||||
}
|
||||
|
||||
uint64_t test_vcvtp_u64_f64(float64_t a) {
|
||||
// CHECK: test_vcvtp_u64_f64
|
||||
// CHECK: fcvtpu {{d[0-9]+}}, {{d[0-9]+}}
|
||||
return (uint64_t)vcvtp_u64_f64(a);
|
||||
}
|
||||
|
||||
int32_t test_vcvts_s32_f32(float32_t a) {
|
||||
// CHECK: test_vcvts_s32_f32
|
||||
// CHECK: fcvtzs {{s[0-9]+}}, {{s[0-9]+}}
|
||||
|
@ -168,12 +120,6 @@ int64_t test_vcvtd_s64_f64(float64_t a) {
|
|||
return (int64_t)vcvtd_s64_f64(a);
|
||||
}
|
||||
|
||||
int64_t test_vcvt_s64_f64(float64_t a) {
|
||||
// CHECK: test_vcvt_s64_f64
|
||||
// CHECK: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}
|
||||
return (int64_t)vcvt_s64_f64(a);
|
||||
}
|
||||
|
||||
uint32_t test_vcvts_u32_f32(float32_t a) {
|
||||
// CHECK: test_vcvts_u32_f32
|
||||
// CHECK: fcvtzu {{s[0-9]+}}, {{s[0-9]+}}
|
||||
|
@ -185,9 +131,3 @@ uint64_t test_vcvtd_u64_f64(float64_t a) {
|
|||
// CHECK: fcvtzu {{d[0-9]+}}, {{d[0-9]+}}
|
||||
return (uint64_t)vcvtd_u64_f64(a);
|
||||
}
|
||||
|
||||
uint64_t test_vcvt_u64_f64(float64_t a) {
|
||||
// CHECK: test_vcvt_u64_f64
|
||||
// CHECK: fcvtzu {{d[0-9]+}}, {{d[0-9]+}}
|
||||
return (uint64_t)vcvt_u64_f64(a);
|
||||
}
|
||||
|
|
|
@ -5616,12 +5616,6 @@ float64_t test_vcvtd_f64_s64(int64_t a) {
|
|||
return vcvtd_f64_s64(a);
|
||||
}
|
||||
|
||||
float64_t test_vcvt_f64_s64(int64_t a) {
|
||||
// CHECK: test_vcvt_f64_s64
|
||||
// CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
|
||||
return vcvt_f64_s64(a);
|
||||
}
|
||||
|
||||
float32_t test_vcvts_f32_u32(uint32_t a) {
|
||||
// CHECK: test_vcvts_f32_u32
|
||||
// CHECK: ucvtf {{s[0-9]+}}, {{s[0-9]+}}
|
||||
|
@ -5634,12 +5628,6 @@ float64_t test_vcvtd_f64_u64(uint64_t a) {
|
|||
return vcvtd_f64_u64(a);
|
||||
}
|
||||
|
||||
float64_t test_vcvt_f64_u64(uint64_t a) {
|
||||
// CHECK: test_vcvt_f64_u64
|
||||
// CHECK: ucvtf {{d[0-9]+}}, {{d[0-9]+}}
|
||||
return vcvt_f64_u64(a);
|
||||
}
|
||||
|
||||
float32_t test_vrecpes_f32(float32_t a) {
|
||||
// CHECK: test_vrecpes_f32
|
||||
// CHECK: frecpe {{s[0-9]+}}, {{s[0-9]+}}
|
||||
|
@ -11231,12 +11219,6 @@ float64_t test_vabdd_f64(float64_t a, float64_t b) {
|
|||
return vabdd_f64(a, b);
|
||||
}
|
||||
|
||||
float64_t test_vabd_f64(float64_t a, float64_t b) {
|
||||
// CHECK-LABEL: test_vabd_f64
|
||||
// CHECK: fabd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
|
||||
return vabd_f64(a, b);
|
||||
}
|
||||
|
||||
int64x1_t test_vuqadd_s64(int64x1_t a, uint64x1_t b) {
|
||||
// CHECK-LABEL: test_vuqadd_s64
|
||||
return vuqadd_s64(a, b);
|
||||
|
|
|
@ -391,8 +391,8 @@ static void ParseTypes(Record *r, std::string &s,
|
|||
int len = 0;
|
||||
|
||||
for (unsigned i = 0, e = s.size(); i != e; ++i, ++len) {
|
||||
if (data[len] == 'P' || data[len] == 'Q' || data[len] == 'U' ||
|
||||
data[len] == 'H' || data[len] == 'S' || data[len] == 'T')
|
||||
if (data[len] == 'P' || data[len] == 'Q' || data[len] == 'U'
|
||||
|| data[len] == 'H' || data[len] == 'S')
|
||||
continue;
|
||||
|
||||
switch (data[len]) {
|
||||
|
@ -480,9 +480,9 @@ static std::string GetNarrowTypestr(StringRef ty)
|
|||
static char ClassifyType(StringRef ty, bool &quad, bool &poly, bool &usgn) {
|
||||
unsigned off = 0;
|
||||
// ignore scalar.
|
||||
if (ty[off] == 'S' || ty[off] == 'T')
|
||||
if (ty[off] == 'S') {
|
||||
++off;
|
||||
|
||||
}
|
||||
// remember quad.
|
||||
if (ty[off] == 'Q' || ty[off] == 'H') {
|
||||
quad = true;
|
||||
|
@ -897,14 +897,9 @@ static void InstructionTypeCode(const StringRef &typeStr,
|
|||
|
||||
static char Insert_BHSD_Suffix(StringRef typestr){
|
||||
unsigned off = 0;
|
||||
|
||||
// Don't include the BHSD suffix.
|
||||
if (typestr[0] == 'T')
|
||||
return 0;
|
||||
|
||||
if (typestr[off++] == 'S') {
|
||||
while (typestr[off] == 'Q' || typestr[off] == 'H'||
|
||||
typestr[off] == 'P' || typestr[off] == 'U')
|
||||
if(typestr[off++] == 'S'){
|
||||
while(typestr[off] == 'Q' || typestr[off] == 'H'||
|
||||
typestr[off] == 'P' || typestr[off] == 'U')
|
||||
++off;
|
||||
switch (typestr[off]){
|
||||
default : break;
|
||||
|
@ -932,8 +927,7 @@ static bool endsWith_xN(std::string const &name) {
|
|||
/// MangleName - Append a type or width suffix to a base neon function name,
|
||||
/// and insert a 'q' in the appropriate location if type string starts with 'Q'.
|
||||
/// E.g. turn "vst2_lane" into "vst2q_lane_f32", etc.
|
||||
/// Insert proper 'b' 'h' 's' 'd' if prefix 'S' is used. Do not insert size
|
||||
/// suffix if the prefix 'T' is used.
|
||||
/// Insert proper 'b' 'h' 's' 'd' if prefix 'S' is used.
|
||||
static std::string MangleName(const std::string &name, StringRef typestr,
|
||||
ClassKind ck) {
|
||||
if (name == "vcvt_f32_f16" || name == "vcvt_f32_f64")
|
||||
|
|
Loading…
Reference in New Issue