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[Hexagon] Adding memb instruction. Fixing whitespace in test from 224730. 

llvm-svn: 224735
This commit is contained in:
Colin LeMahieu 2014-12-22 21:40:43 +00:00
parent 9a6f2836db
commit 4b1eac4dda
6 changed files with 32 additions and 30 deletions
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4
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
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@ -407,7 +407,7 @@ SDNode *HexagonDAGToDAGISel::SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl) {
if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed;
else if (LoadedVT == MVT::i32) Opcode = Hexagon::LDriw_indexed;
else if (LoadedVT == MVT::i16) Opcode = Hexagon::LDrih_indexed;
else if (LoadedVT == MVT::i8) Opcode = Hexagon::LDrib_indexed;
else if (LoadedVT == MVT::i8) Opcode = Hexagon::L2_loadrb_io;
else llvm_unreachable("unknown memory type");
// Build indexed load.
@ -612,7 +612,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
if (TII->isValidAutoIncImm(LoadedVT, Val))
Opcode = zextval ? Hexagon::POST_LDriub : Hexagon::POST_LDrib;
else
Opcode = zextval ? Hexagon::L2_loadrub_io : Hexagon::LDrib;
Opcode = zextval ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io;
} else
llvm_unreachable("unknown memory type");

13
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
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@ -81,7 +81,7 @@ unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
case Hexagon::LDriw:
case Hexagon::LDrid:
case Hexagon::LDrih:
case Hexagon::LDrib:
case Hexagon::L2_loadrb_io:
case Hexagon::L2_loadrub_io:
if (MI->getOperand(2).isFI() &&
MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
@ -684,9 +684,8 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
case Hexagon::LDriuh_indexed:
return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
case Hexagon::LDrib:
case Hexagon::L2_loadrb_io:
case Hexagon::L2_loadrub_io:
case Hexagon::LDrib_indexed:
return isUInt<6>(MI->getOperand(2).getImm());
case Hexagon::POST_LDrid:
@ -1130,7 +1129,7 @@ isValidOffset(const int Opcode, const int Offset) const {
return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
(Offset <= Hexagon_MEMH_OFFSET_MAX);
case Hexagon::LDrib:
case Hexagon::L2_loadrb_io:
case Hexagon::STrib:
case Hexagon::L2_loadrub_io:
return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
@ -1363,10 +1362,8 @@ isConditionalLoad (const MachineInstr* MI) const {
case Hexagon::LDrih_cNotPt :
case Hexagon::LDrih_indexed_cPt :
case Hexagon::LDrih_indexed_cNotPt :
case Hexagon::LDrib_cPt :
case Hexagon::LDrib_cNotPt :
case Hexagon::LDrib_indexed_cPt :
case Hexagon::LDrib_indexed_cNotPt :
case Hexagon::L2_ploadrbt_io:
case Hexagon::L2_ploadrbf_io:
case Hexagon::LDriuh_cPt :
case Hexagon::LDriuh_cNotPt :
case Hexagon::LDriuh_indexed_cPt :

27
llvm/lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -1543,6 +1543,7 @@ multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
}
let accessSize = ByteAccess, isCodeGenOnly = 0 in {
defm loadrb: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, 0b1000>;
defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>;
}
@ -1586,10 +1587,6 @@ multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
}
let addrMode = BaseImmOffset, isMEMri = "true" in {
let accessSize = ByteAccess in {
defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
}
let accessSize = HalfWordAccess in {
defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
@ -1603,7 +1600,7 @@ let addrMode = BaseImmOffset, isMEMri = "true" in {
}
def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
(LDrib ADDRriS11_0:$addr) >;
(L2_loadrb_io AddrFI:$addr, 0) >;
def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)),
(L2_loadrub_io AddrFI:$addr, 0) >;
@ -1662,10 +1659,6 @@ multiclass LD_Idxd2<string mnemonic, string CextOp, RegisterClass RC,
}
let addrMode = BaseImmOffset in {
let accessSize = ByteAccess in {
defm LDrib_indexed: LD_Idxd2 <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
11, 6>, AddrModeRel;
}
let accessSize = HalfWordAccess in {
defm LDrih_indexed: LD_Idxd2 <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
12, 7>, AddrModeRel;
@ -1683,7 +1676,7 @@ let addrMode = BaseImmOffset in {
let AddedComplexity = 20 in {
def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
(LDrib_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
(L2_loadrb_io IntRegs:$src1, s11_0ExtPred:$offset) >;
def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
(L2_loadrub_io IntRegs:$src1, s11_0ExtPred:$offset) >;
@ -1760,16 +1753,16 @@ let hasCtrlDep = 1, hasSideEffects = 0, addrMode = PostInc in {
}
def : Pat< (i32 (extloadi1 ADDRriS11_0:$addr)),
(i32 (LDrib ADDRriS11_0:$addr)) >;
(i32 (L2_loadrb_io AddrFI:$addr, 0)) >;
// Load byte any-extend.
def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
(i32 (LDrib ADDRriS11_0:$addr)) >;
(i32 (L2_loadrb_io AddrFI:$addr, 0)) >;
// Indexed load byte any-extend.
let AddedComplexity = 20 in
def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
(i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
(i32 (L2_loadrb_io IntRegs:$src1, s11_0ImmPred:$offset)) >;
def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
(i32 (LDrih ADDRriS11_1:$addr))>;
@ -3773,7 +3766,7 @@ def : Pat <(i64 (zextloadi1 (HexagonCONST32 tglobaladdr:$global))),
// Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
let AddedComplexity = 10 in
def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
(i32 (A2_and (i32 (LDrib ADDRriS11_0:$addr)), (A2_tfrsi 0x1)))>;
(i32 (A2_and (i32 (L2_loadrb_io AddrFI:$addr, 0)), (A2_tfrsi 0x1)))>;
// Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = A2_sxtw(Rss.lo).
def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
@ -3856,7 +3849,7 @@ def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
// Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
def : Pat<(i1 (load ADDRriS11_2:$addr)),
(i1 (C2_tfrrp (i32 (LDrib ADDRriS11_2:$addr))))>;
(i1 (C2_tfrrp (i32 (L2_loadrb_io AddrFI:$addr, 0))))>;
// Map for truncating from 64 immediates to 32 bit immediates.
def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
@ -4026,12 +4019,12 @@ def : Pat <(i64 (sext (i1 PredRegs:$src1))),
// Convert sign-extended load back to load and sign extend.
// i8 -> i64
def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
(i64 (A2_sxtw (LDrib ADDRriS11_0:$src1)))>;
(i64 (A2_sxtw (L2_loadrb_io AddrFI:$src1, 0)))>;
// Convert any-extended load back to load and sign extend.
// i8 -> i64
def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
(i64 (A2_sxtw (LDrib ADDRriS11_0:$src1)))>;
(i64 (A2_sxtw (L2_loadrb_io AddrFI:$src1, 0)))>;
// Convert sign-extended load back to load and sign extend.
// i16 -> i64

2
llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
View File

@ -163,7 +163,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
(MI.getOpcode() == Hexagon::LDrid) ||
(MI.getOpcode() == Hexagon::LDrih) ||
(MI.getOpcode() == Hexagon::LDriuh) ||
(MI.getOpcode() == Hexagon::LDrib) ||
(MI.getOpcode() == Hexagon::L2_loadrb_io) ||
(MI.getOpcode() == Hexagon::L2_loadrub_io) ||
(MI.getOpcode() == Hexagon::LDriw_f) ||
(MI.getOpcode() == Hexagon::LDrid_f)) {

4
llvm/test/CodeGen/Hexagon/cext-check.ll
View File

@ -29,9 +29,9 @@ return:
}
define i32 @cext_test2(i8* %a) nounwind {
; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}+##1023)
; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}+{{ *}}##1023)
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##300000)
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}+##1024)
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}##1024)
; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##6000)
entry:
%tobool = icmp ne i8* %a, null

12
llvm/test/MC/Disassembler/Hexagon/ld.txt
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@ -1,5 +1,17 @@
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
0xf1 0xc3 0x15 0x91
# CHECK: r17 = memb(r21 + #31)
0x91 0xdd 0x15 0x41
# CHECK: if (p3) r17 = memb(r21 + #44)
0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x43
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) r17 = memb(r21 + #44)
0x91 0xdd 0x15 0x45
# CHECK: if (!p3) r17 = memb(r21 + #44)
0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x47
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = memb(r21 + #44)
0xf1 0xc3 0x35 0x91
# CHECK: r17 = memub(r21 + #31)
0xf1 0xdb 0x35 0x41